Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

511 · 2025-06-16T13:39:56-0400

We also don't get detailed articles like old AT no crap just plain info

Thunder 57 · 2025-06-16T13:47:10-0400

511 said:
We also don't get detailed articles like old AT no crap just plain info

I miss the deep dives. I wonder they largely stopped because people don't care, or if companies give out less details about architecture these days? I'm inclined to think the latter. Still C&C manages to get into detail though.

511 · 2025-06-16T13:48:25-0400

Thunder 57 said:
I miss the deep dives. I wonder they largely stopped because people don't care, or if companies give out less details about architecture these days? I'm inclined to think the latter. Still C&C manages to get into detail though.

Same Deep Dives are the best but in modern era clickbait/misinformation sells but not Correct Info.

Doug S · 2025-06-16T14:35:57-0400

Thunder 57 said:
I miss the deep dives. I wonder they largely stopped because people don't care, or if companies give out less details about architecture these days? I'm inclined to think the latter. Still C&C manages to get into detail though.

It may have had more to do with the cost of keeping the people talented enough to properly do those deep dives. When you have guys getting hired away by big tech firms or starting their own sites there wasn't going to be anything they could do to keep them. If they don't have anyone capable of matching that and/or they aren't willing or able to pay enough to hire one you those deep dives go away. Now you have someone like Geekerwan who could do those but he why should he work for someone else when he can site up his own site/channel and keep everything for himself? And not have any boss telling him what to review or worrying that him criticizing the wrong company will hurt the site's advertising revenue!

Apple has never given out much info about their architecture, but today Apple's architectures are MORE open today simply because having it on Mac makes it a lot more accessible than when it was only available on a locked down smartphone platform.

Fjodor2001 · 2025-06-16T15:15:04-0400

Thunder 57 said:
That's not surprising. That scenario is great for E-cores and that is no secret. From just above in the article:

It would seem that is very much an "it depends" scenario. Intel has made great progress here, just look at the 14900k scaling in that graph.

Well, it seems to be a surprise to some that were concerned about NVL-S not having 300+ W TDP.

Then regarding the test I linked to, I agree that the E cores shine in that scenario. But since it's an MT test, the P cores will be running as well in parallel, which means they're of course also included in the measurement. So they must also have much better perf/watt when not being pushed to max frequency.

Finally, for NVL-S 52C there will be 16P + 32E + 4LPE cores. So if E cores is what makes Arrow Lake-S perform well in MT scenarios when not pushed to max frequency, I think we can expect NVL-S to also perform well in such scenarios since it'll have a lot of E cores.

AcrosTinus · 2025-06-16T17:48:50-0400

If the leaks are true, the SKU design for the Ultra 7 suggests that the two compute die theory might not be true. I really think that we will see basically this in a ring:

4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE
4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE

16stops, elongated die, an imaginary evolution of the current one.

dullard · 2025-06-16T18:14:58-0400

AcrosTinus said:
If the leaks are true, the SKU design for the Ultra 7 suggests that the two compute die theory might not be true. I really think that we will see basically this in a ring:

4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE
4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE

16stops, elongated die, an imaginary evolution of the current one.

I don't follow your logic. Could you explain more?

What if Intel had these chips:
A: (8P + 16E) sold as the top Core Ultra 5.
B: (6P + 8E) with some cores disabled due to a defect, sold as the bottom Core Ultra 5.
C: (4P + 8E) with even more cores disabled due to defects, sold as the top Core Ultra 3.
D: (4P + 4E) with even more cores disabled due to defects, sold as the bottom Core Ultra 3.

Then why wouldn't the Core Ultra 9 be two of the A chips, (8P + 16E) + (8P + 16E) = 16P + 32E?

And then why wouldn't the Core Ultra 7 be one of the A chips and one of the B chips, (8P + 16E) + (6P + 8E) = 14P + 24E?

There would be no reason to combine the lower performing chips into a top tier CPU.

eek2121 · 2025-06-16T18:19:01-0400

AcrosTinus said:
If the leaks are true, the SKU design for the Ultra 7 suggests that the two compute die theory might not be true. I really think that we will see basically this in a ring:

4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE
4xE--2xP--4xE--2xP--2xP--4xE--2P--4xE

16stops, elongated die, an imaginary evolution of the current one.

While I won't bet on current rumors being right, everything I've seen indicates that Intel is planning (or did plan) a dual chiplet part.
They may not even be using a ring bus at all, or they could be using a ring of rings, mesh, or some other topography.

At any rate, a dual chiplet design would most certainly be an Ultra 9 part, not an ultra 7 part, if is part of the Core series at all (it could be Xeon or something).

Fjodor2001 · 2025-06-16T18:19:47-0400

Regarding LPE core on NVL, what are we expecting to be used for that? Will it e.g. be a downclocked E core, or completely different arch compared to P and E cores?

AcrosTinus · 2025-06-16T18:34:14-0400

dullard said:
I don't follow your logic. Could you explain more?

What if Intel had these chips:
A: (8P + 16E) sold as the top Core Ultra 5.
B: (6P + 8E) with some cores disabled due to a defect, sold as the bottom Core Ultra 5.
C: (4P + 8E) with even more cores disabled due to defects, sold as the top Core Ultra 3.
D: (4P + 4E) with even more cores disabled due to defects, sold as the bottom Core Ultra 3.

Then why wouldn't the Core Ultra 9 be two of the A chips, (8P + 16E) + (8P + 16E) = 16P + 32E?

And then why wouldn't the Core Ultra 7 be one of the A chips and one of the B chips, (8P + 16E) + (6P + 8E) = 14P + 24E?

There would be no reason to combine the lower performing chips into a top tier CPU.

I am just guessing, they would just have a completely different die for the lower products, the same for the current generation. In the current one, the Ultra 9 and 7 have the same die, the others don't. On some SKUs the heatspreader is even different.

I am most likely wrong but that is what I image, because how would the base die look like ? Would there just be a dummy die or a blank like on single CCD Ryzens?

AcrosTinus · 2025-06-16T18:40:02-0400

eek2121 said:
While I won't bet on current rumors being right, everything I've seen indicates that Intel is planning (or did plan) a dual chiplet part.
They may not even be using a ring bus at all, or they could be using a ring of rings, mesh, or some other topography.

At any rate, a dual chiplet design would most certainly be an Ultra 9 part, not an ultra 7 part, if is part of the Core series at all (it could be Xeon or something).

You might be right, a mainstream mesh by intel might be the simplest explanation.

LightningZ71 · 2025-06-16T19:24:49-0400

I still wonder, especially now that the designs are node agnostic, why can't the smaller, lower performance core dies be on an older, less expensive node? For instance, their 4P +8e die could be implemented on a dense library Intel3 chip that would fit the space of the 8p+16e chip.

jpiniero · 2025-06-16T19:30:11-0400

LightningZ71 said:
I still wonder, especially now that the designs are node agnostic, why can't the smaller, lower performance core dies be on an older, less expensive node? For instance, their 4P +8e die could be implemented on a dense library Intel3 chip that would fit the space of the 8p+16e chip.

The only Intel node with any real volume is 10 nm and friends.

DavidC1 · 2025-06-16T20:37:53-0400

Fjodor2001 said:
Regarding LPE core on NVL, what are we expecting to be used for that? Will it e.g. be a downclocked E core, or completely different arch compared to P and E cores?

Downclocked E core. They don't have a third uarch. Not only you need additional monetary and personnel for such new development, they need additional research to reach a point where they find a good balance with it. The first Atom uarch sucked. The Out of Order Atom improved so much that it offered all the benefits of the new uarch without negatives such as increased power and area.

Meteorlake's dual Crestmont was too slow for even browsing/Youtube duties. So making a slower core than the E core makes no sense.

LightningZ71 said:
I still wonder, especially now that the designs are node agnostic, why can't the smaller, lower performance core dies be on an older, less expensive node? For instance, their 4P +8e die could be implemented on a dense library Intel3 chip that would fit the space of the 8p+16e chip.

I assume that's because the cores still benefit from new nodes in both power and area while IO transistors such as in the SoC tile stopped scaling a while ago. That means for cores it's not really beneficial in terms of cost to spend extra time and money porting to an older process.

DavidC1 · 2025-06-16T20:43:51-0400

Io Magnesso said:
Right, N3B is much more denser, But that's the case with the most dense configuration...
I still don't know what kind of N3B configuration of Intel is using in Arrow Lake...

What are you talking about? N3B is straight up better than Intel 4. There's no competition.

Lion Cove/P cores just suck, that's it. You can compare to AMD. Zen 5 is on a worse node and the core area is significantly smaller. And Zen 4 was way better than Golden Cove that's used in both Alderlake and Refreshlake(also re-Refreshlake)

Their P core vs E cores are just like Pentium 4 vs Banias. I'm pretty sure some made the argument that Pentium 4 clocks much higher. Yes, but at some point you have to ask.

Gracemont vs Golden Cove made sense. Skymont vs Lion Cove absolutely does not. We went from being 40% perf/clock gap in Int + 70% difference in FP + 40% clock difference + SMT to 10% perf/clock in Int and FP + 24% clock difference without SMT. The decrease in ratio from ~4:1 to ~3:1 can be explained entirely by huge increase in FP performance.

There's a legitimate reason for their hybrid strategy. They literally cannot put same amount of P cores as AMD without consuming power like a RTX 5090 video card.

Io Magnesso · 2025-06-16T21:01:10-0400

DavidC1 said:
What are you talking about? N3B is straight up better than Intel 4. There's no competition.

Lion Cove/P cores just suck, that's it. You can compare to AMD. Zen 5 is on a worse node and the core area is significantly smaller. And Zen 4 was way better than Golden Cove that's used in both Alderlake and Refreshlake(also re-Refreshlake)

Their P core vs E cores are just like Pentium 4 vs Banias. I'm pretty sure some made the argument that Is it an HP cell?Pentium 4 clocks much higher. Yes, but at some point you have to ask.

Gracemont vs Golden Cove made sense. Skymont vs Lion Cove absolutely does not. We went from being 40% perf/clock gap in Int + 70% difference in FP + 40% clock difference + SMT to 10% perf/clock in Int and FP + 24% clock difference without SMT. The decrease in ratio from ~4:1 to ~3:1 can be explained entirely by huge increase in FP performance.

There's a legitimate reason for their hybrid strategy. They literally cannot put same amount of P cores as AMD without consuming power like a RTX 5090 video card.

I'm sorry it's hard to understand
What I'm talking about is how Intel used the N3B cell library? I just wondered
Is it an HP cell I wanted to say that Sorry for my lack of English

Io Magnesso · 2025-06-16T21:03:11-0400

The larger the heat spreader of the CPU, the easier it is to cool it…

DavidC1 · 2025-06-16T21:08:43-0400

Io Magnesso said:
I'm sorry it's hard to understand
What I'm talking about is how Intel used the N3B cell library? I just wondered
Is it an HP cell I wanted to say that Sorry for my lack of English

At 5.7GHz clocks it has to be the best cell. Arrowlake would have been a lot worse if it wasn't for Skymont.

adroc_thurston · 2025-06-16T21:18:23-0400

DavidC1 said:
Arrowlake would have been a lot worse if it wasn't for Skymont.

ARL problem is that it sucks in games, and Skymont does nothing there.

Io Magnesso · 2025-06-16T22:01:08-0400

adroc_thurston said:
ARL problem is that it sucks in games, and Skymont does nothing there.

I think Skymont can play a solid role...

adroc_thurston · 2025-06-16T22:07:32-0400

Io Magnesso said:
I think Skymont can play a solid role...

in games? lmao no.

Io Magnesso · 2025-06-16T22:22:08-0400

adroc_thurston said:
in games? lmao no.

Well, the E-core is not very useful in games.
However, do you think PCs are only used for games? lol

adroc_thurston · 2025-06-16T22:36:58-0400

Io Magnesso said:
However, do you think PCs are only used for games?

DIY DT ones? Yea.

511 · 2025-06-16T22:50:59-0400

adroc_thurston said:
ARL problem is that it sucks in games, and Skymont does nothing there.

If only we got 5Ghz Skymonts like the guy running in games

Io Magnesso said:
I'm sorry it's hard to understand
What I'm talking about is how Intel used the N3B cell library? I just wondered
Is it an HP cell I wanted to say that Sorry for my lack of English

Most likely 3-2 FinFlex

adroc_thurston · 2025-06-16T22:54:24-0400

511 said:
If only we got 5Ghz Skymonts like the guy running in games

Idk how that would salvage horrible cachemem perf.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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