He had even more rumors for today. 12 more PCI-E 5.0 lanes (36 total) and 12 more PCI-E 4.0 lanes (16 total) compared to Arrow Lake. https://wccftech.com/intel-nova-lak...00-memory-support-natively-36-pcie-5-0-lanes/Very nice, above the 7200 claim I heard earlier
It's a bigger L3 pile, no 3D stacking.Wonder what the extra cache SKU is and when it comes out? stacked? Or all in one die (hopefully P Core only, imagine either 16P Coyote/Griffin Cove Cores w/ 144+ MB of Cache in a single die, would be sick).
Having 3D stacking is a feature checklist. Whether it performs better is significantly up to engineering, which Arrowlake failed at.From @g0ld3nm4ng0 on twitter. The bLLC SKUs are still there though not shown in this pic. I’m worried for NVL-S L3 performance if it hasn’t been fixed since it’s another CT and not 3DS.
Having 3D stacking is a feature checklist. Whether it performs better is significantly up to engineering, which Arrowlake failed at.
So how the NVL cache performs is dependent on implementation. It could be worse than Arrowlake, or better than it regardless whether it's 3D or not. When Intel was top of the hill, their caches were fantastic even with a humongous size. No 3D necessary.
Case in point: Lakefield. Had ALL the theoretical advantages for a super low power SoC. In reality it had battery life like a plain jane -Y part, while performing worse in many cases(it was so bad that Tremont value chip was just as fast as the P core in Lakefield).
They gave same lame excuses as Robert Hallock with Arrowlake about why Lakefield performed bad. Needed new BIOS updates... blah blah.
somehow they learned how to do it starting with Zen.
He probably gave them some ideas on how to do that but since he wasn't there to oversee it, they bungled up his plans.I think Jim Keller probably directed the Interconnect and Chiplet when he was at Intel.
Well, it's much more constructive to put it on the market and get feedback, even if the degree of perfection is fair, rather than not putting it on the market for fear. I think Zuckerberg from META (Facebook) said something similar.He probably gave them some ideas on how to do that but since he wasn't there to oversee it, they bungled up his plans.
It's so telling that they went through almost a dozen Sapphire Rapids steppings to fix it but for consumer chips, they were like, ah just release it with warts and all. They won't notice! And they are somewhat right. Meteor Lake sold and Arrow Lake is selling too. Not as well as they hoped but at least it's not something as bad as Atom or Celeron.
If Zuckbro said that, it makes sense from a software perspective but for hardware, that's a very, very expensive thing to do. I remember a teacher telling us in a programming class that in the early days, computing time was expensive so you had to really think hard about your code and had to run it in your brain and be very sure that it would run flawlessly otherwise you would fall behind someone who was better at mentally simulating code execution.Well, it's much more constructive to put it on the market and get feedback, even if the degree of perfection is fair, rather than not putting it on the market for fear. I think Zuckerberg from META (Facebook) said something similar.
It's 2t and it's not that hard on N2p.I'm having a hard time believing Intel can put 16P cores, 32E cores, and 4 LPE on a die at less than $1000 and still turn a profit?
They don't need to do anything.Zen 6 would need at least 32/64 to keep up.
Well, you can't miss the cost...If Zuckbro said that, it makes sense from a software perspective but for hardware, that's a very, very expensive thing to do. I remember a teacher telling us in a programming class that in the early days, computing time was expensive so you had to really think hard about your code and had to run it in your brain and be very sure that it would run flawlessly otherwise you would fall behind someone who was better at mentally simulating code execution.
The PCI-E Config is really niceHe had even more rumors for today. 12 more PCI-E 5.0 lanes (36 total) and 12 more PCI-E 4.0 lanes (16 total) compared to Arrow Lake. https://wccftech.com/intel-nova-lak...00-memory-support-natively-36-pcie-5-0-lanes/
Sapphire Rapids went through losing the entire validation team. EVERYONE.It's so telling that they went through almost a dozen Sapphire Rapids steppings to fix it but for consumer chips, they were like, ah just release it with warts and all. They won't notice! And they are somewhat right. Meteor Lake sold and Arrow Lake is selling too.
Well... they are also very cheap, that's why they are "bad". Why would you expect otherwise?Not as well as they hoped but at least it's not something as bad as Atom or Celeron.
L1 latencies are also significantly function of architecture and design. All the other levels aren't so dependent on that.Intel used to be the king of cache. AMD just couldn't compete, with few exceptions like K7's excellent L1 that was used again and again.
They were purpose made to be bad so if someone got one due to bad finances, they would dream of someday getting a "real" CPU like a Pentium or a Core i3.Well... they are also very cheap, that's why they are "bad". Why would you expect otherwise?
Sapphire's project started around 2015, and the 10nm delay may have had an effect, but since it Xeon after Ice Lake, it didn't really matter as a result. I've read it in some media, but in an interview with an engineer in charge of Sapphire The engineer said, "I've gotten too late because I've packed too many functions"He probably gave them some ideas on how to do that but since he wasn't there to oversee it, they bungled up his plans.
It's so telling that they went through almost a dozen Sapphire Rapids steppings to fix it but for consumer chips, they were like, ah just release it with warts and all. They won't notice! And they are somewhat right. Meteor Lake sold and Arrow Lake is selling too. Not as well as they hoped but at least it's not something as bad as Atom or Celeron.
Originally, Sapphire was aiming for a degree of perfection like Emerald Rapids.Sapphire's project started around 2015, and the 10nm delay may have had an effect, but since it's Xeon after Ice Lake, it didn't really matter as a result. I've read it in some media, but in an interview with an engineer in charge of Sapphire The engineer said, "I've gotten too late because I've packed too many functions"
It's kind of like 10nm... I also hear that it was delayed by trying to improve the performance considerably due to changes in the material of 10nm and so on.
(Although it was delayed, the performance and transistor density became quite high in the 10nm generation)
Perhaps one of the reasons for the delay is the fact that it is packed with too many functions or that you tried to improve the performance to the extreme.
The damn accelerators. Some idiot executive's pipedream of CPU as a service.Perhaps one of the reasons for the delay is the fact that it is packed with too many functions or that you tried to improve the performance to the extreme.
Are you talking about AMX? A AVX-like standing position for matrix and tensor processing, so to speak, which is often used for neural processing…The damn accelerators.
Are you talking about AMX?