Well 18A/AP are design compatible also it's a similar case with N3E and P.It comes down to a Raichu rumor. Then people extrapolate it to be 18A. The timing makes sense especially if 18A is not being as utilized as Intel hoped by 3rd parties. 18A would have 29% fewer masks and if the equipment is underutilized this is a win-win for salvaging the underutilized equipment and personnel. I suspect Intel would rather sell that equipment time, but this is their backup option.
ARC Celestial (Xe3P) may be a game-changing GPU architecture for Intel
ARC Celestial may be a game-changing GPU architecture for Intel, using Intel lithography tech and new their Xe3P architecture.overclock3d.net
ARC Celestial (Xe3P) may be a game-changing GPU architecture for Intel
ARC Celestial may be a game-changing GPU architecture for Intel, using Intel lithography tech and new their Xe3P architecture.overclock3d.net
This goes into way more detail than I could: https://chipsandcheese.com/p/looking-ahead-at-intels-xe3-gpu-architectureA game changer ? Why ?
I think you over-estimate the wafer cost. ArrowLake's compute tile is about 114 mm2, NVL with same cache size should be smaller than ARL. I am expecting around 100 mm2. Don't forget the improvement of SRAM density. That's why Zen 6c able to fit in 128MB in single die. With estimated of 80% yield, Intel could get 500 dies per wafer. Even at $30,000 per wafer, cost per die is about $60 only. No doubt they are costly compared to Ryzen 7950X as explained by Ian here, but with selling price under $1000, Intel still has many margins to dangle with.I'm having a hard time believing Intel can put 16P cores, 32E cores, and 4 LPE on a die at less than $1000 and still turn a profit?
I am skeptical of the validity of the data of this leak. Skeptical yet hopeful...
Your concern seems valid, and I also don't believe AMD who has launched higher core count before Intel will let Intel overtake the performance crown. That's why I suspect AMD is working to bring Zen6c (32-core with 128MB L3 cache) to desktop lineup. I know it is not in the roadmap yet but kind of make sense. We shall see...If this turns out to be reality it will be a CB destroyer, Zen 6 would need at least 32/64 to keep up.
Yes, this "feels" like an MLID sort of "leak."
Zen6 is N2/N2P.I think you over-estimate the wafer cost. ArrowLake's compute tile is about 114 mm2, NVL with same cache size should be smaller than ARL. I am expecting around 100 mm2. Don't forget the improvement of SRAM density. That's why Zen 6c able to fit in 128MB in single die. With estimated of 80% yield, Intel could get 500 dies per wafer. Even at $30,000 per wafer, cost per die is about $60 only. No doubt they are costly compared to Ryzen 7950X as explained by Ian here, but with selling price under $1000, Intel still has many margins to dangle with.
I have created table with the leaks about NovaLake-S desktop lineup in the frontpage, Core Ultra 9 sure looks like badass in term of thread numbers. With bLLC, Intel might bring back Extreme Edition to justify high price tags, what do you think?
Your concern seems valid, and I also don't believe AMD who has launched higher core count before Intel will let Intel overtake the performance crown. That's why I suspect AMD is working to bring Zen6c (32-core with 128MB L3 cache) to desktop lineup. I know it is not in the roadmap yet but kind of make sense. We shall see...
How did you come up with the idea that Ryzen 7 will be a dual chiplet SKU with 24 cores?I have created table with the leaks about NovaLake-S desktop lineup in the frontpage
Nah they won't bother with the suggestion here on zen6c. Same reason I always say, np one cares about the number of cores past a certain point. AMD won't need to increase core count to match noval lakes large number of cores. That nova lake part is a bit...weird unless it also has the fastest binned single coresI think you over-estimate the wafer cost. ArrowLake's compute tile is about 114 mm2, NVL with same cache size should be smaller than ARL. I am expecting around 100 mm2. Don't forget the improvement of SRAM density. That's why Zen 6c able to fit in 128MB in single die. With estimated of 80% yield, Intel could get 500 dies per wafer. Even at $30,000 per wafer, cost per die is about $60 only. No doubt they are costly compared to Ryzen 7950X as explained by Ian here, but with selling price under $1000, Intel still has many margins to dangle with.
I have created table with the leaks about NovaLake-S desktop lineup in the frontpage, Core Ultra 9 sure looks like badass in term of thread numbers. With bLLC, Intel might bring back Extreme Edition to justify high price tags, what do you think?
Your concern seems valid, and I also don't believe AMD who has launched higher core count before Intel will let Intel overtake the performance crown. That's why I suspect AMD is working to bring Zen6c (32-core with 128MB L3 cache) to desktop lineup. I know it is not in the roadmap yet but kind of make sense. We shall see...
there is nothing weird with 24Core NVL tbh it's just they are using 2 compute dies to connect to HUBNah they won't bother with the suggestion here on zen6c. Same reason I always say, np one cares about the number of cores past a certain point. AMD won't need to increase core count to match noval lakes large number of cores. That nova lake part is a bit...weird unless it also has the fastest binned single cores
Thanks for making the table. I am suspicious of two of your Nova Lake Core Ultra 7 core counts though. How do you get those specific combinations?I have created table with the leaks about NovaLake-S desktop lineup in the frontpage, Core Ultra 9 sure looks like badass in term of thread numbers. With bLLC, Intel might bring back Extreme Edition to justify high price tags, what do you think?
there is no 6+8 Tile btw it's just a binned version and since 2P cores has to be disabled like a 4E Core Cluster it is possible to makeThanks for making the table. I am suspicious of two of your Nova Lake Core Ultra 7 core counts though. How do you get those specific combinations?
Do you think for the top Core Ultra 7 that Intel will put its best two tested tiles together (8P + 16E) and (8P + 12E) and just disable two P cores simply for price differentiation? That seems odd. I would assume that instead the top Core Ultra 7 would be this combination of tiles (8P + 16E) and (6P + 8E) = (14P + 24E).
Similar argument for your lower Core Ultra 7. Wouldn't it make more sense for Intel to combine two (6P + 8E) tiles to get (12P + 16E)? Your listing of (12P + 24E) means that Intel uses a perfectly good 8P chip and disables 2P cores simply for price differentiation. Wouldn't it make more sense to use more of the 6P chips up?
View attachment 126322
Of course it is dependent on binning. I was assuming people knew the 6P+8E was a binned 8P+16E chip.there is no 6+8 Tile btw it's just a binned version and since 2P cores has to be disabled like a 4E Core Cluster it is possible to make
6+12 and 8+16 = 14+28
6+8 and 6+16 = 12+24
it's totally dependent on binning
I was assuming reverse 🤣Of course it is dependent on binning. I was assuming people knew the 6P+8E was a binned 8P+16E chip.
Yeah maybe they are preliminary even they won't know the SKU List unless they run more wafersThe two I highlighted in red would be chips that are not on the table.
I've always wondered. Do they hide the titanium/platinum samples and keep it for themselves or extremely rich people? There needs to be more transparency regarding binning. Like the percentage of titanium, platinum, golden, silver, very good, good and fair samples.Yeah maybe they are preliminary even they won't know the SKU List unless they run more wafers
Super cool leak.View attachment 110886
With Pat pretty much confirm the existence of Nova Lake; let's started new thread about Nova Lake, the successor of Arrow Lake.
View attachment 110887
Even though Nova Lake is still two years away (currently target for Q4 2026 release), my source has provided more information below:
- Once again, Intel will change the tile methodology of Nova Lake. The IMC no longer inside CPU tile, it is going to be integrated inside SoC tile. Nova Lake's SoC tile also going to integrate GPU as well. Since GPU is not considered priority for desktop and high-performance laptop chip, it makes sense for Intel to integrate GPU into SoC tile. That's mean Intel is able to reduce the total amount of tiles from four to three. Yep, considered this as ARL v2.0.
- Higher NGU (new term for NoC of SoC tile) and ring clocks should fix the memory latency issues, we shall see.
- The top-end SKU of NVL-SK / S / HX will integrate V-cache similar to AMD's X3D. My source can't confirm the amount of L3 cache but the recent leaks about 144MB seems valid. This is going to be fourth tile on the base tile of SoC.
- Currently, NVL platform will support up to 128-bit DDR5-8000, the same memory speed AMD would support for upcoming Zen6.
- Both Intel's NVL and AMD's Zen6 are targeting for Q4-2026 release.
- As for process node, well Intel will definitely try to use IFS but as Pat said there are going to have some tiles that are made by TSMC, we should hear more in the future.
Preliminary Leaks of Intel Nova Lake and Zen6 Lineup
Nova Lake - S CPU Tiles CPU Cores 4 LPe Standard TDP L3 Cache bLLC 144MB ? Zen 6 CPU Tiles CPU Cores 2 LPe + SMT L3 Cache X3D 96MB ? Ryzen 9 (Zen 6c) ? N2 x 1 32 64 T 128 MB 224 MB 28 56 T Core Ultra 9 N2 x 2 16 + 32 48 T 150 W 72 MB 216 MB Ryzen 7 N3P x 2 24 48 T 96 MB 192 MB Core Ultra 7 14 + 28 42 T 150 W 20 40 T 12 + 24 36 T 150 W 16 32 T Core Ultra 5 N2 x 1 8 + 16 24 T 125 W 36 MB Ryzen 5 N3P x 1 12 24 T 48 MB 144 MB 8 + 12 20 T 125 W 10 20 T 6 + 8 14 T 125 W Core Ultra 3 18A x 1 4 + 8 12 T 65 W 18 MB Ryzen 3 (Zen 5) ? N4P x 1 8 16 T 32 MB 4 + 4 8 T 65 W 6 12 T
Bonus: AMD's Zen6
Beside higher core count, Zen6 is still targeting for Q4-2026's release; same timings as NVL.
Zen6's CCD will be fabbed by N3 family, most likely N3P.
That's all I know atm, enough to start the discussion about upcoming Intel's Nova Lake.
I would go a bit further than you. I'm having a hard time believing Intel can turn a profit.I'm having a hard time believing Intel can put 16P cores, 32E cores, and 4 LPE on a die at less than $1000 and still turn a profit?
I am skeptical of the validity of the data of this leak. Skeptical yet hopeful...
If this turns out to be reality it will be a CB destroyer, Zen 6 would need at least 32/64 to keep up.
Yes, this "feels" like an MLID sort of "leak."
I think that the failure of ARL and to a much lesser extent Zen 2 shows that there is a great deal of problems going to chiplets .... and that Intel is not past those problems .....yet.What specifically is hard about it? It is actually quite easy to do. Putting multiple tiles on a CPU is fairly standard practice now. It gets harder to do well -- but that does not seem to be your argument here.
Mine too Hulk. I don't doubt that they can make it, I doubt they can make money doing it.Seems like an HEDT amount of transistors for a CPU priced for client. "Hard" to make economically viable is what I'm thinking.
NVL has AVX 10.2 with a 256bit data path IIRC. It will still be at a 30% disadvantage to even Zen 5's implementation .... but much better than not having it at all!Bruh now their is no reason to hate on E cores in NVL you got AVX 10.2 aka 512 and improved cores as well as APX it's just nitpicking at this point.
It's not that costly tbh like you people are thinking they just need to not mess up the architecture like ARL.Mine too Hulk. I don't doubt that they can make it, I doubt they can make money doing it.
No it has full 512 vector length for the data path I am not sure.NVL has AVX 10.2 with a 256bit data path IIRC. It will still be at a 30% disadvantage to even Zen 5's implementation .... but much better than not having it at all!
So two E-cores will essentially perform as well as a single P-core if the instruction throughput is same? Maybe less as the cache pressure on the E-core cluster cache will be higher. So it may end up as being just OK AVX-512 performance compared to the all P-core performance of Zen 5 or 6.It is possible they will do 512b paths on P-cores and 256b paths on E-cores.
SIR @Kepler_L2 is the ST Perf true cause if it's meh