20 step pipeline Pentium 4

[thelanx]

I read the article about the pentium 4 when it came out. Anand was talking about how a 20 step pipeline would make the clock speed faster. I don't get it. Does the processor go through 1 step for every clock cycle? If that is so, wouldn't the processor be the same regardless of clock speed because you get the same amount done as with a processor with a lower clock speed but one that does more?

 

[thelanx]

bump

 

[da loser]

here

 

[DaddyG]

Its actually a 20 stage pipeline. Each stage performs a 'unit of work' on the instruction. The implication behind more stages is that each stage does less work so you can run the clock at a higher frequency. Some simple instructions have a kinda fast-track through the pipe as all instructions are not created equal.

 

[WyattBurp]

thelanx

All current machines use pipelines, basically a sort of assembly line for instructions. Each instruction takes the same amount of clocks to pass through the pipe. However, the effects of each instructions may and often do occur earlier and in some cases in stages. Once the pipe is full and is maintained, the effective through-put is one instruction per clock. This is the advantage a pipeline architecture offers.

The problem with short pipelines is that some complex instructions take too long. Such instructions must be handled outside of the pipe with enormous time penalties. Especially as more users want to engage in more complex operations. To prevent that, companies like Intel have avoided such instructions, but that limits the full potential of their machine.

To summarize, the longer pipe doesn't really make the machine faster for today. But it will make it faster for tomorrow and it will make it more powerful.

Just my 2cents

--Wyatt

 

[DaddyG]

Wyatt,

Reconsider yout comment on instructions executing 'outside' the pipe. Don't believe thats true. Complex instructions take more pipeline cycles, they simply don't move through the pipe. These instructions will normally stay in the execution unit for extra cycles, but some instructions need more cycles in the I-unit if the operands are indirectly addressed. Register to Register instructions are the simplest, they can often be completed in the I-unit without any E-unit time.. Also remember that in the case of current Intel and AMD processor the instuctions executed are the X86 equivalent micro-ops not the actual x86 instuction.

 

[BurntKooshie]

DaddyG - actually, Intel uses uopos (microops), and while AMD did use something similar, they just called them risc86 ops for their K6 family. Athlons actually translate instructions into MACRO ops - the exact opposite of Intel. Instead of breaking x86 instructions up into more smaller instructions (or in many cases, directly 1 to 1), AMD's take MORE than one x86 instruction to make one macrop.

 

[DaddyG]

Good catch BurntK.

Many years ago when I worked at Amdahl developing mainframes, we used the term Macrocode. Actually, the Marketeers coined the name, in development we called it ESP. The basic concept, was very similar to what is happening today. The I-unit recognized certain instructions and fed the rest of the pipe an equivalent instruction stream. In the case of highly complex instructions, the cpu entered a special mode for both the I-unit decode and the E-unit execution. At the time, this was quite revolutionary, not surprised that its had a trickle down effect.