64 core EPYC Rome （Zen2）Architecture Overview？

[Vattila]

That is, an "APU" would just have a different kind of IO chip with a GPU in it.

What about MCM packaging cost and capacity? Is it feasible in the mainstream?

 

[Gideon]

I see very little chance that this will happen.

One of the big reasons AMD wants to architect it's product lines like they are doing them is that the cost of mask sets per chip has more than doubled every new process node. On 14nm, they touted only having 2 distinct chips and serving the entire market from APUs to massive servers with them as a major win. Now, they have had to pay even more for a single design. My bet is that if they truly are going with a small, 8-core chiplet with a separate IO die, it's because they intend to serve their entire product line, from laptops through desktops to servers with it. That is, an "APU" would just have a different kind of IO chip with a GPU in it.

This is why i was leaning on Naples having an "integrated" GPU. Whether as a 3rd chiplet (in which case it's optional), part of the IO chiplet, or part of the monolithic chip (that goes down to 15W TDP notebook parts). I just don't see AMD will do different 7nm designs for Consumer desktop and mobile with the mask-costs

 

[Atari2600]

I wonder if it's just a controller or if there is another l4 cache in there?!

All rumours (and I suppose, logic) say there is a substantial L4 in there.

I suspect the L4 will (at least) mirror all L3 entries to more quickly service requests for data that would reside on other CCX L3.

 

[Glo.]

is AMD releasing a 7nm AM4 CPU with more than 8 Cores? it looks like their dies are all 8 cores still, so I wouldn't expect a huge change for desktop CPUs at least...


the Epyc with twice the dies and the controller chip is looking very interesting, I wonder if it's just a controller or if there is another l4 cache in there?!

8 core, and up .

Yes. AM4 platform will see 12, and 16 cores, and most likely Zen 2 CPUs will start from 8C/8T Ryzen 3 CPUs - simply will double core count of Zen and Zen+, on AM4.

 

[Atari2600]

Yes. AM4 platform will see 12, and 16 cores, and most likely Zen 2 CPUs will start from 8C/8T Ryzen 3 CPUs - simply will double core count of Zen and Zen+, on AM4.

I was going to say, I'm not sure how much value I seen in 16 cores being fed by 2 channels of DDR4.

But, upon reflection, the performance of the 2990 WX would suggest that 32 cores can be fed quite effectively by 4 channels for these workloads. Obviously not ideal for many other workloads, but good enough to justify its existence.

If AMD can improve the memory controller such that it will run with DDR4-4000, then I'd guess a 16C Zen2 on a dual channel memory setup is definitely worthwhile.


edit: Ooops - I had rejigged this post a few times before issuing it, and I removed what workloads I was talking about - content creation - blender/cinebench kinda stuff. Not memory intensive.

 

[Abwx]

I was going to say, I'm not sure how much value I seen in 16 cores being fed by 2 channels of DDR4.

But, upon reflection, the performance of the 2990 WX would suggest that 32 cores can be fed quite effectively by 4 channels for these workloads. Obviously not ideal for many other workloads, but good enough to justify its existence.

If AMD can improve the memory controller such that it will run with DDR4-4000, then I'd guess a 16C Zen2 on a dual channel memory setup is definitely worthwhile.

2990WX is not comparable since there s more inter dies nodes, 6 for this SKU and only one for a 2 die chip at 8C/CCX.

 

[Tuna-Fish]

I was going to say, I'm not sure how much value I seen in 16 cores being fed by 2 channels of DDR4.

But, upon reflection, the performance of the 2990 WX would suggest that 32 cores can be fed quite effectively by 4 channels for these workloads. Obviously not ideal for many other workloads, but good enough to justify its existence.

If AMD can improve the memory controller such that it will run with DDR4-4000, then I'd guess a 16C Zen2 on a dual channel memory setup is definitely worthwhile.

Another thing that helps is larger caches. SRAM scales better than logic when going from 14nm->7nm, so it makes a lot of sense to increase the amount of L3 cache per core. Doubling last level cache at current sizes gives something like 10%-30% reduction in miss rates, depending on workload. Or to think it in another way, assuming 20% improvement in hit rate, doubling the usable L3 buys you 25% more bandwidth.

 

[Glo.]

I was going to say, I'm not sure how much value I seen in 16 cores being fed by 2 channels of DDR4.

But, upon reflection, the performance of the 2990 WX would suggest that 32 cores can be fed quite effectively by 4 channels for these workloads. Obviously not ideal for many other workloads, but good enough to justify its existence.

If AMD can improve the memory controller such that it will run with DDR4-4000, then I'd guess a 16C Zen2 on a dual channel memory setup is definitely worthwhile.

We do not know anything about Zen 2 performance from memory bandwidth. AMD may have changed here a lot to not run into any bottleneck.

 

[HurleyBird]

So now that the 8 + 1 configuration is all but confirmed, the particulars of the controller chip make for pretty interesting speculation. Large L4 cache? Large integrated GPU with beefy double precision? Some combination of the two?

I also sort of expect that we'll see more granular iteration now, so, for example, some sort of tick-tock between the controller chip and CPU cores. Might we also see controller chips that are specific to some industry or another? For example, a controller with several channels of HBM for bandwidth constrained tasks? And of course the same is true for the CPU dies, which could end up similarly specialised (eg. attach an FPGA instead). Really fascinating to think of the applications and implications for such a modular approach.

The realistic part of me thinks that, regardless of the huge potential that this approach affords, AMD just doesn't have enough resources to go after even a small portion of the possibilities. On the other hand, if they get third parties to develop their own compatible modular chips, things could get very interesting.

 

[HurleyBird]

We do not know anything about Zen 2 performance from memory bandwidth. AMD may have changed here a lot to not run into any bottleneck.

It's probably a safe assumption that Zen 2 will improve memory bandwidth utilisation to some degree, but the magnitude of that improvement has a large possible range.

 

[dnavas]

Might we also see controller chips that are specific to some industry or another?

Yeah, I assume that ZenX refers to integrated heterogenous compute units of some kind -- GPU, ML, 4:2:2 decoders (hah hah, no, I don't expect that -- I'd like that, I just don't expect it). I assume those would be aimed at some specialized industry....

 

[beginner99]

So now that the 8 + 1 configuration is all but confirmed

Nothing is confirmed and the hype dreaming in this thread are even more extreme than there were for Polaris and then Vega and we all know how that turned out. With AMDs limited budget I very much doubt they will be first to 7nm, first to do chiplets while at the same time magically increase IPC and clocks and it all comes together perfectly with no delay. I will be hugely impressed if they pull this off.

 

[maddie]

Nothing is confirmed and the hype dreaming in this thread are even more extreme than there were for Polaris and then Vega and we all know how that turned out. With AMDs limited budget I very much doubt they will be first to 7nm, first to do chiplets while at the same time magically increase IPC and clocks and it all comes together perfectly with no delay. I will be hugely impressed if they pull this off.

?????????

First to X86 7nm? Check
Increased clocks? Pretty much a given in transitioning to 7nm. Check
Increased IPC? Direct statement from AMD attesting to same. Check
Chiplets? Unproven, but the leaks are starting to snowball.
No delay? What's considered a delay, if they're already showing it to some clients.

What am I missing, that you're seeing?

 

[beginner99]

What am I missing, that you're seeing?

It probably won't be chiplets and more like current zeppelin die. Or if they are there is some penalty that needs to be paid especially for client / gaming be it high price, delays or whatever. Simply my opinion. And hence I could be completely wrong. The as said I will be hugely impressed also by gigantic risk taking deciding on such a design (chiplets) probably at least 3 years ago.

And no higher clocks are for sure not guaranteed going to a newer process. See intel with their 14nm++++ outperforming anything 10nm they can field in the next couple years. However yes in this specific case it is very likely true as the previous process was a lower power mobile process with a pretty low hard limit. So yeah higher clocks and higher IPC are a must. But it's not like that is for free just because new process.

 

[HurleyBird]

Right now, there are just too many leaks from too many sources pointing at 8+1 that it's almost certainly true. In any case, we should know for sure in a few days.

 

[beginner99]

Right now, there are just too many leaks from too many sources pointing at 8+1 that it's almost certainly true. In any case, we should know for sure in a few days.

8+1 could be 8 cores plus 1 CU as iGPU for client. This iGPU would make sense for OEM and in general people that need CPU power but no graphics power. Like I would at work.

 

[HurleyBird]

That hypothetical is pretty absurd.

 

[tamz_msc]

8+1 could be 8 cores plus 1 CU as iGPU for client. This iGPU would make sense for OEM and in general people that need CPU power but no graphics power. Like I would at work.

This speculation thread and the rumors associated with it is regarding a possible server configuration, not client.

 

[DrMrLordX]

I was going to say, I'm not sure how much value I seen in 16 cores being fed by 2 channels of DDR4..

I'm kind of wondering if AMD can expand AM4 to allow 4-channel configurations for newer boards that support it. If the pinouts are there, I see no reason why mobo manufacturers couldn't produce AM4 2-channel boards for legacy products and 4-channel boards (4x DIMM slots only) for newer 16c chips. Only issue I see is that, typically, when you have quad-channel configs, you see DIMM slots position on either side of the socket to reduce trace lengths (I guess). AM4 boards currently have 4 slots off to the right of the CPU socket.

Of course if you were to try to use a 16c quad-channel AM4 CPU in an older X470 or X370 boards, you'd have to disable half the RAM channels and run in in a dual-channel configuration.

 

[dacostafilipe]

If AMD goes with chiplets, they will certainly have a different dies for server and desktop, so everything discussed here (rome rumours) could have zero impact on the AM4 platform.

 

[Atari2600]

I'm kind of wondering if AMD can expand AM4 to allow 4-channel configurations for newer boards that support it. If the pinouts are there, I see no reason why mobo manufacturers couldn't produce AM4 2-channel boards for legacy products and 4-channel boards (4x DIMM slots only) for newer 16c chips.

Are the pin outs there? I thought they weren't and that is why we had TR4.

 

[The Stilt]

I'm kind of wondering if AMD can expand AM4 to allow 4-channel configurations for newer boards that support it. If the pinouts are there, I see no reason why mobo manufacturers couldn't produce AM4 2-channel boards for legacy products and 4-channel boards (4x DIMM slots only) for newer 16c chips. Only issue I see is that, typically, when you have quad-channel configs, you see DIMM slots position on either side of the socket to reduce trace lengths (I guess). AM4 boards currently have 4 slots off to the right of the CPU socket.

Of course if you were to try to use a 16c quad-channel AM4 CPU in an older X470 or X370 boards, you'd have to disable half the RAM channels and run in in a dual-channel configuration.

If you are asking if there are currently > 280 unused pins in AM4 package required for the two additional memory channels, the answer is no.

 

[krumme]

So Canard was right.
Congrats on the 1 year birthday for this rumour.
Always spot on so early. Crazy.

 

[moinmoin]

Might we also see controller chips that are specific to some industry or another?

Customize the controller chip to your liking, go crazy with existing CCX and CU chiplets. Should be a nice selling point for their semi-custom business.

 

[DrMrLordX]

Are the pin outs there? I thought they weren't and that is why we had TR4.

I think there are some, but . . .

If you are asking if there are currently > 280 unused pins in AM4 package required for the two additional memory channels, the answer is no.

Aw shucks. Nevermind then!