Originally posted by: dmens
fact is D0 is only a packaging revision, and not a die revision
D0 is an all-layer stepping, which is a die revision, i guess. the latter is not the term i would use.
also, a packaging revision (pin swap?) is even more drastic and costly than a die revision and is to be avoided at all costs.
You are familiar with this document right?
Originally posted by: chizow
My take on it is that engineers and manufacturer's goal is to produce the best possible chip, period. They're not telling electrons to work 75% as hard on one wafer and Extreme overtime on another, or to mail it in once they finish enough of the L3 to meet whatever chip bin they're shooting for, or letting their monkey go home early once its picked enough shiny heat spreaders.
Sure there's going to be binning and chip modification to meet market segment demands, but one of the fundamental principals in overclocking is that demand is going to be very low on the high-end parts with a supply that should theoretically all be the same until validated and binned otherwise. I'm clearly hedging my bets that there's more "high-end" parts that could be sold as such, but are down-binned to meet demand.
That's misinformation. Every cpu is binned, but they are not binned by voltage like you think, they are binned by wattage. If a cpu does not fit the TDP envelope at 3.2G, it becomes a 940, if it does not fit the envelope at 2.93G it becomes a 920. The same way, a 975 needs to fit the envelope at 3.33G. TDP is largely determined by voltage, so the lower the voltage required the lower the TDP will be, for a 975's TDP to equal that of a 965, the VID has to actually be lower on the 975, because the clock speed is higher so the current draw is higher.
Originally posted by: aigomorla
but my conclusions are coming from 2 ES samples.
C0/C1 ES
vs.
D0 ES.
And if the models behave simular, then i have great expitations on the D0.
Did you forget my 965 was also an ES?
http://i125.photobucket.com/al.../aigomorla/Final-1.jpg
Again, the chip you have now is a better bin. It has much more to do with that, than the fact that it's D0.
Originally posted by: harbin
Just want to know, is my C0 920 LinX 20 run @4.0g with 1.19V Vcore any good comparing with your D0 result? Or I need do more to approve D0 is nothing new?
With HT on? I doubt it, I'd love to see a screenshot.
Originally posted by: OCguy
I think you are the one who may be wrong.
Even woldfale C1 ---> E0 made a big difference.
Intel doesn't say so, and frankly I believe them more than a handful of forum members with carefully picked 975 chips. I guess you'll find out when 920 D0s hit retail.