AM2 X2 5000+

[the Chase]

I'm glad to have this kernal of info on the chip and grateful that the OP has shared it with us. But anyone notice how quiet he's been? Hopefully not in trouble for "spilling the beans". Any more you can tell us about this boshuter??

 

[secretanchitman]

so bottom line: AM2 X2 5000+ runs at a 266FSB instead of 200FSB yielding a 2-5% increase. alright, cool.

chase, you are right...he has been quiet lately...

 

[Skott]

I'm still of the opinion its better to just wait and see an actual production chip test that gives us all the info and specs.

 

[bongsteen]

my opinion is am2 will be good if you got no dual core rig yet. swithching to dual core might give more flexibility in the long run.

 

[formulav8]

A Higher HTT Mhz Speed would decrease the memory controller latency. But I can't see it making that much of a difference in actual performance. But the increase would be there since the memory controller would would be using a lesser multiplyer, which therefore its running at a higher internal speed. So, a increase could be shown in the right situations. If they do this higher hht mhz speed, it would evidentally be to try and overcome the higher DDR2 latency.


Jason

 

[AkumaX]

i wonder why amd went from 200htt to 333htt (what happened to 266htt?)

 

[ooeric]

mhz is mhz.. it makes no damn difference.
my x2 im using right now is still faster.

guess what??

am2 is the basically same as a64 in instructions..

stfu pwnd. next topic.

 

[Viditor]

Originally posted by: Fox5

Just because the impact is lessened doesn't mean it isn't there.

To clarify something here...

On a FSB architecture, all signals from the CPU go to the Northbridge and from there to memory, PCIE, other CPUs, and the Southbridge. The speed at which the Northbridge runs is essentially the FSB. In addition, because ALL signals go through the Northbridge, it must be very fast and very wide to accomodate all of that traffic. The speed at which the Northbridge can move signals is therefore the bottleneck of this model as it runs much slower than the CPU.

On AMD's architecture the Northbridge is incorporated into the chip itself, and the different signals use several different paths.
1. The memory has it's own connection via a cHT (coherent HT) link.
2. The PCIE and Southbridge also have their own connection via a standard HT link
3. Other CPUs also have their own cHT link
4. The cHT links and the standard HT links can and do run at different speeds from one another.
5. Because there is so much less data on each cHT and HT link than there is on a FSB, bandwidth is a MUCH smaller issue.

The bottleneck on an AMD platform is therefore the IPC of the core itself and not it's signal path (as it would be in a FSB model).

Of course there are caveats here...
It will help if you think of each link as a transceiver. With a transceiver, you must convert sound vibrations into radio waves and then convert them back again.
Similarly, the CPU must convert the data to transmit over the cHT link and then back again (this is true for all memory controllers). What governs the speed of this transaction (in the case of AMD) is 2 things...how fast can you convert and how fast the memory can "hear".
1. Since this is a new "transceiver" for AMD, it's conversion efficiency is much less than the older DDR Rev E one (IIRC it's ~53% for the DDR2 and ~90% for DDR).
2. DDR2 must perform additional steps (latency) for it to "hear" properly, so increasing the clockspeed is the only way (so far) to bring it into parity with DDR.

Another caveat is the fact that (as Furen pointed out) the transceivers run at the same rate as the CPU, so they must be "tuned" to accomodate the speed requirements of the transmission and reception. If you change the speed of the CPU, you must also retune the transceivers...
Whether the base rate is 200 or 333 doesn't matter except that retuning is done differently...

 

[the Chase]

Thanks for taking the time to teach us(me) something. That was a good read. I wonder if he was correct with the cache size of 2 x 1MB for the 5000 model and what would that mean for the others? All getting more L2 cache or just this one? I know it doesn't make a huge difference perf. wise for the A64 chips but it can't hurt.

 

[PingSpike]

Originally posted by: Acanthus

Originally posted by: guoziming
um... so if AM2's HTT speed is higher than 200, would that mean increased performance...?

no

Thats what I thought...so why is this such a big deal? As I understand it, the cpu clock/HTT speed is pretty much just a piece that other buses actually derive their speed from. Its not a FSB.

All I can see this doing is making overclocking a bigger pain in the ass. Which would steer me away from AM2 more then anything. Am I missing something here?

And on a related note...I thought all memory runs on the divider on the A64. There's no such thing as "in sync" right?

 

[chilled]

This doesn't make much sense. The CPU was manufactured in Week 4 of this year. Anand reviewed an AM2 chip only this month and pretty much confirmed that all specs were status quo. I find it hard to believe how AMD would be able to spring such a surprise so soon before release.

The specs for this 5000+ would give an extra 66MHz at least, with a faster HTT speed. This means they may give a 3% advantage over the presumed 5000+ that Anand indicated was to be released. If this is the case we would assume it has a 8% advantage over current chips for these ratings.

I'll believe it when it's released...

 

[Mogadon]

It's called an NDA(Non Disclosure Agreement). AMD may have only given them the chip if they agreed not to release certain specs, it happens all the time with all hardware reviewers.

But yeah, i'll wait until it's released to make any assumptions, I guess it's fun to speculate though ... .