Gen-Z is the closet to IF.
Then, you need to look at CCIX:
The no bridges/switches comes from ringing like HTX(Hypertransport's PCIe).
Last edited:
Gen-Z is the closet to IF.You speak as if this is a given and has already been detailed. Where does this operate in this capacity today outside of CPU socket linking?
The diagram below shows a mixed PCIe Root Complex and Gen-Z Requester / Responder protocol stack inside of a SoC. This “dual-boot” application example shows how new CPU / SoC designs can be made to allow for both PCIe root complex and Gen-Z protocols sharing the same gigabit-transceivers. The SoC firmware can configure the IO interface to be a mixed PCIe Root Complex / Gen-Z complex, a dual port PCIe Root Complex, or a dual port Gen-Z complex. This flexibility allows SoC designers to leverage the Gen-Z fabric for specific applications while allowing for support of legacy PCIe components within the system.
As noted earlier, one of the biggest attractions of CCIX is its compatibility with PCI Express, and in fact CCIX’s cache coherency protocol can be carried over any PCI Express link running 8GT/s or faster. The highest data rate specified by PCI Express 4.0 is 16GT/s, which works out to around 64GB/s of total bidirectional bandwidth on a 16-lane link, but some members of the CCIX Consortium needed even more bandwidth. They determined that by raising the transfer rate to 25GT/s, a CCIX link could approach 100GB/s under the same conditions. This led to a CCIX feature known as Extended Speed Mode (ESM). Since PCI Express is owned by a different standards body, the CCIX Consortium chose a clever mechanism to allow compatibility between ESM-capable components and PCI Express components. Two CCIX components wishing to communicate with each other proceed through a normal PCI Express link initialization process (generally a hardware autonomous process) to the highest mutually supported PCI Express speed. From that point, software running on the host system can interrogate CCIX-specific configuration registers and determine if both components are ESM-capable, and if so, identify their highest supported speeds. That software then programs other CCIX-specific registers on both components to map PCI Express link speed(s) to CCIX ESM link speed(s). From that point forward, link negotiation would be for CCIX ESM speed(s), so by forcing a link retraining, the two components could now communicate as quickly as 25GT/s.
8C CCX confirmed. GG AMD, well played. RIP intel
If only we could zoom and enhance...
C-Ray is very favorable for Zen.AMD showed C-Ray comparison of 1x 64 Rome against 2x 28 core intel Xeon. AMD finished the render 7% faster with 14% more cores. They said Rome was prototype system and not the highest performance (clocks) they'll achieve with the part.
Confirmed where?
In the image of Lisa holding the die? 8 chiplets for 64 core part. How many cores per chiplet?Confirmed where?
AMD used a Rome prototype that was likely running at very low clock . The difference will be very noticeable.C-Ray is very favorable for Zen.
Seems they're leaving a lot on the table if that's the case given that Zen2 is PCIE 4.0 and all of the other goodies : infinity fabric CPU/GPU? Is this a point in which AMD will start to focus moreso on profits and segmentation where the pro CPUs/GPUs start to have clear features distinguished from consumer line? What's this event spell for consumer line? We have 8 cores per CCX now... Will consumer side see a doubling too or just a shrink? Any potential for exotic add-ons to the chiplet like HBM? GPU complex? What will AMD do w/ all of the newly available space on consumer Zen2? What does consumer Zen2 look like?
In the image of Lisa holding the die? 8 chiplets for 64 core part. How many cores per chiplet?
Gen-Z is the closet to IF.
Then, you need to look at CCIX:
The no bridges/switches comes from ringing like HTX(Hypertransport's PCIe).
Core per chiplet != core per CCXIn the image of Lisa holding the die? 8 chiplets for 64 core part. How many cores per chiplet?
A wide(r) core, finally
The next big question I have is how much cache does that IO die have? To host all that IO, it needs a large circumference. So a lot would fit, even at 14nm.
Wow, AMD un-integrated the northbridge.
I think it will still be 16 MB L3 cache within each chiplet with a larger L4 cache within the IO die. Someone mentioned that the IO die will need to have a large perimeter to interface with each of the chiplets, even more so if there are 8 of them. The interior space within this IO die can be used for a large, shared L4 cache.
Well all the suggested layouts where wrong. In fact 4 chiplets are further away. Got to wonder if that has a tiny performance impact? or in power consumption due to longer traces?
To be fair most experimenting with layouts did say that fitting 8 chiplets next to IO die would be hard or not possible due to size and they were right.
And for sure no interposer assuming this isn't a mock-up.
In the live stream. The top Rome chip is 8x 8 core CPUs + 1x I/O chip
Yeah, the chiplets are huge. Didn't expect that.
Yeah, something tells me there will be a lot of exotic packages going into the near future with this new product launch. I actually predict that the 14nm central I/O die + chiplet will be present far more than people think as it opens up the way for interesting new APU configurations/etc... and its cheap being 14nm... Further, it allows for far more reuse. It will be cut down no doubt from the server version but there's no reason not to see this even on a 8core CCX rollout.In a way yes, but, while the clock speeds and memory bandwidth increases mean that Vega 20 should be able to substantially outperform Vega 64 (while consuming less power), it comes with huge extra cost, so it'd be pointless to market it to gamers. Just look at the backlash over NVidia's pricing. Now imagine AMD tries selling a card that offers maybe 2080Ti performance but costs even more (possibly a LOT more, like $2K+), and doesn't have the ray-tracing capability (possibly AMD could tailor some of the other stuff for that, but it would be half-baked, even moreso than Nvidia's RTX features are). It'd be a dud and pointless for gamer market. On top of that, I think Navi should offer similar gaming performance to Vega 20, and be much less expensive to produce (especially when factoring in the HBM). I expect that Navi should offer close to the CU count of Vega 64/Vega 20, but should have improvements to the pipeline, and clock speeds should be similar if not higher than Vega 20. Navi should make Vega 20 pointless for gamers. Because of the memory bandwidth (it'll probably be 2-3x the memory bandwidth of Navi) it might be able to offer more performance still, but it'd probably cost almost 10x what Navi based cards do.
Yeah the GPU IF link is pretty much a pro feature right now. Games just don't need that bandwidth yet, and need it even less now that multi-GPU like Crossfire/SLI are practically deprecated in modern games. Although if it could perhaps target latency instead it would probably help games. And if they do start the mGPU as monolithic move, or even just the single GPU per eye for VR/AR, that might change, but PCIe 3.0 should be enough for that for now, and they might have PCIe 4 support. And then PCIe 5 is not far off (2020, maybe 2021 for AMD to have it in consumer stuff).
I definitely see AMD doing GPU chiplets, especially for APUs (they'll still have a small singular die, but it'll lag behind, and it'll be aimed at low cost systems). We'll see on stuff like HBM since its still pretty expensive. Its a possibility in the future. But I think the chiplet design is more about higher end markets where their customers want more specialized hardware and the ability to have things tailored to their needs. It has benefits lower down, but this is more about offering the big players like Facebook, Google, Microsoft, Amazon and others the ability to add their own custom stuff (like Google's Tensor Processing Unit), or to mix and match based on the use.
That looks like 4 chiplets to me. Two 8 core CCX?
13,2b transistors @ 331mm2 for vega 7nm.
Water cooled Vega 64 had 12.5B transistors and did 13.7TFLOPS @510mm2
So 5.6% more transistors and 7.3% more theoretical performance with 35% smaller die.
Not bad.
Vega 20 is better than I thought it would be.
I actually predict that the 14nm central I/O die + chiplet will be present far more than people think as it opens up the way for interesting new APU configurations/etc... and its cheap being 14nm... Further, it allows for far more reuse. It will be cut down no doubt but there's no reason not to see this even on a 8core CCX rollout.
What's the timing on this screen grab? It's going to be my new smug profile pic on the interwebs
If only we could zoom and enhance...
Yeah, something tells me there will be a lot of exotic packages going into the near future with this new product launch. I actually predict that the 14nm central I/O die + chiplet will be present far more than people think as it opens up the way for interesting new APU configurations/etc... and its cheap being 14nm... Further, it allows for far more reuse. It will be cut down no doubt from the server version but there's no reason not to see this even on a 8core CCX rollout.
Guys, think. Each Chiplet is separate CCX. If it is 8 Core, From this moment on - CCX has 8 Cores.