Integration is simply a matter of having the die space for additional components -- it's not a question of difficulty.alright
so what about integrating audio and radio processors?
will these be easier?
The problem is small units scale better.And widening the decode/retirement/data bus limits the core scaling. The way I see it, the area growth (front end, retirement, even the bypass between the FMAs) required from moving from a 2x128b to a "true" (see below) 4x128b design is significantly larger, more power hungry, probably less frequency than moving from 2x128b to a 2x256b design. So you can more FP units in a much narrower core... hence better core scaling.
15h is already 4 wide and 30h-4Fh made it 8-wide.Now my question is, what's the front end you would put in to feed this CPU? If you say 4 wide, then for applications that can scale to 256b, you have excess decode width. If you say 2 wide, then you don't get the full utilization of a 4x 128b. Flexibility comes with some overhead. I like reconfigurable stuff, but if you want maximum perf/power and hence efficiency, you have to start targeting.
Possibly via HSAIL. AMD might also extend AMD64s ISA to include the ARM ISA and GPU ISA at a much later time. That way the ISA it self is physically Heterogeneous.so are they trying to move the floating point operations over to the gpu?
The problem is small units scale better.Internally the FMA units in Bulldozer to Steamroller are all 64-bit in size. Smaller units are more efficient and less power hungry than bigger units.
15h is already 4 wide and 30h-4Fh made it 8-wide.
what do you guys think the prospects for integrating x86 and arm cores are?
What benefit would you get with that idea?
None. What do you want ARM cores to do that x86 cores can't?what do you guys think the prospects for integrating x86 and arm cores are?
As far as I know, none.What benefit would you get with that idea?
Why would it have to be ARM cores? I think it already something exists, and it's called Xeon Phi. Big.Little, if that's what you mean, might in certain cases be a possibility, but I don't really see the benefits of that. To me it just seems like a marketing thing designed by ARM to justify integrating gazillions of cores onto a small, thermally bounded SoC.that is what i am asking about
so integrating a small number of powerful cores with a large number of more efficient cores would be what i am thinking about. what benefits would there be to this?
would the gpu just do anything the arm cores might?
the arm cores are more powerful than the gpu cores per calculation unit right?
so are they trying to move the floating point operations over to the gpu?
Why not use 15h and 16h side by side then?
Quad-core Steamroller/Excavator + Quad-core Jaguar/Puma
big.LITTLE isnt a solution. Its a hotfix for companies with cores unable to run proper low power operations as well as scale in performance when needed. Qualcomm and Apple for example isnt doing big.LITTLE.
And x86 CPUs certainly dont need it.
I'd actually like to see a low-mid range APU with a pair of ARM cores on board for running Android/ChromeOS as well as Windows without having to reboot or run a VM.
Something like a Quad Steamroller/Excavator with a pair of A53 cores, yet it would be very niche but would be perfect for AIO's as a ultra low power mode for basic web browsing/emails etc.
Core scales well over a full order of magnitude. And over its full range, there isn't a single architecture that does better at just 1 point of the TDP curve.No. A single CPU core type can never cover the same frequency range as well as two separate CPU core types, when performance and power consumption is taken into account. But it's already been discussed here.
Core scales well over a full order of magnitude. And over its full range, there isn't a single architecture that does better at just 1 point of the TDP curve.
ARM cores, or any CPU cores, are indeed more powerful than GPU cores (e.g. you need ~100 Phi cores to get a few tflops, but you need thousands of GPU cores).
This is a marketing slide comparing an in-order design to an A15, which isn't really efficient, and we're discussing desktops. It might be interesting though, something like quadcore Goldmont + dualcore Skylake.A Haswell core will never be as power efficient as an ARM7 when running low processing loads.
Check this out for how ARM Cortex-A7 and A-15 relate. A Haswell curve would be even further to the top right than the A15.
But anyway, I think that discussion is out of topic in this thread. I suggest the existing thread on that topic is woken up instead if needed.
Thank you for you clarification, there doesn't seem to be a lot of difference then.Don't fall for GPU marketing madness. In GPU marketing language, each Xeon Phi core would be referred to as 16 "cores"- it has 16 SIMD lanes, meaning it can operate on 16 elements in parallel. As such the Phi would be a 960 "core" GPU.
Thank you for you clarification, there doesn't seem to be a lot of difference then.
Well the Xeon is lacking the dedicated hardware that a GPU has, like hardware texture sampling units, rasterization engine, and so on. It's a purely compute oriented beast.
I find it hilarious when people dismiss one companies slides as PR but using another companies PR slides to showcase what they want.
I mean the number of flops/core is about the same if I take your 960 Xeon cores number.