AMD Carrizo APU Details Leaked

[mrmt]

Why do you think IPC gains can't come with energy utilization optimization?

I'm not sure whether I could explain myself, but I didn't say that IPC gains will lead to more power consumption. I said that IPC gains might lead to added power consumption *if someone doesn't spend some money to improve power management*. And how AMD can both improve IPC and improve power management at a faster pace than Intel if they have less money for R&D than they had in 2010/2011 and an extra product line to fund? It's simply not possible, because the R&D cost each generation is always bigger than the previous one, unless you restrict your scope by a lot, which would void your IPC gains.

AMD is planning a better a CPU at 65w TDP target. Why doubt them?

Did you follow their track record in the next 8 years? Not really encouraging, is it?

In any case, even AMD marketing department is carefully calibrating the expectations of the market partners here. They are not coming with aggressive marketing schemes, but providing good value proposition to partners, and all the leaks they show points to a more efficient processor with good value, not for a top notch performer, and all the leaks point to that. It will be on 28nm, and will use HDL, which will reduce the top clock speed.

 

[NostaSeronx]

It will be on 28nm, and will use HDL, which will reduce the top clock speed.

High Density Libraries and Ultra High Density Libraries with automated and hand custom designs have shown increases to the clock rate.

What HDL will give consumers over HSL:
+Faster access times
+Higher clock rates
+Lower leakage
+Lower power consumption

 

[el etro]

I'm not sure whether I could explain myself, but I didn't say that IPC gains will lead to more power consumption. I said that IPC gains might lead to added power consumption

 

[mrmt]

What made you confused?

 

[el etro]

What made you confused?

This.

-less(10 or 20 percent lesser) die size, less power consumption at the same performance level;

And why do you think IPC gains will come for free? Making units bigger/more complex also hurts power consumption, which either demands higher TDP or lower clocks. Adding more units even more, so some IPC gains might actually hurt more AMD than it helps.

I'm not sure whether I could explain myself, but I didn't say that IPC gains will lead to more power consumption. I said that IPC gains might lead to added power consumption

IPC gains don't mean more power consumption and can be achieved with reducing the size of the chip too and BDZ arch have many arch Bottlenecks(like memory dependency or data feeding to certain processor parts) to be explored too. It all depends on AMD success on achieving all this.

 

[mrmt]

IPC gains don't mean more power consumption and can be achieved with reducing the size of the chip too and BDZ arch have many arch Bottlenecks(like memory dependency or data feeding to certain processor parts) to be explored too. It all depends on AMD success on achieving all this.

IPC cannot be improved by a die shrinking alone. If you have a X number of transistors arranged in a Y form, why shrinking it to a new node would make the transistors do more work per clock?

One way to improve IPC is to making units bigger/more complex, which means that they will need more transistors and consequently they will consume more power. Another way is to beef up the number of units per core, which will add extra transistors to the core, and that will add more power consumption.

What you are describing as addressing the chip bottlenecks should be achieved by the processes I described above, and I think you can see how this can lead to added power consumption. You can also redesign a given unit to achieve better results with the same transistor budget, but unless you are talking about some poorly optimized chip, it just won't cut it.

 

[Ajay]

Why would people migrating from XP go for AMD? Given that a lot of people and companies are replacing desktops with notebooks, I'd say that people upgrading will mean even less market share for AMD.

Temporary desktop market expansion. A rising tide lifts all boats. Carrizo should be out by the time Win9 is released and will offer plenty of power to the average corporate user. Win9 will be much more appealing to corporation because it can be configured to work as a standard Windows desktop interface. Metro apps will be able to be used in windowed mode on the desktop just like a desktop app as well. It is an ideal transition product (and what Win8 should have been).

It wouldn't 'save' AMD, it just might pump enough money into their coffers and help them make their next play. If they don't have a 'next' play, well, get out the tiny violins.

 

[Ajay]

Using the extra die area for a big fat ESRAM cache could be an interesting choice, but don't forget just how much die area ESRAM takes. About a quarter of the XBox One's die is given over to the 32MB ESRAM, i.e. about 90mm^2. They'd have to bump up the die size a fair bit to fit that on there, even with HDL. EDRAM is more dense, but as far as I'm aware none of the fabs that AMD has access to has that sort of tech- only IBM and Intel.

Still, it's not beyond the realms of possibility. I've said before that a nice big shared LLC would be useful for APU workloads, especially with unified memory.

Thanks for bringing this up. Great idea, probably too expensive for an APU @ 28nm, but much better @ 20nm or less.

The XBox One's APU is designed by AMD, and supposedly, can be built by both TSMC and GFL (I can't recall ATM who is fabbing MS's APU).

I don't know if either fab has the capability to provide E-DRAM for an LLC. IIRC, Micron helped Intel develop their E-DRAM.

 

[Ajay]

Only DDR4 can save the APUs them. AMD is in Intel's game, they don't have the power to introduce different RAM tech to mainstream with good availability.

IIRC, DDR4 does have better streaming performance - so that would make sense (someone here with a better understanding of DDR4 should correct me if I'm wrong)

My bet is that true performance gains in AMD archs will only come after the Bulldozer family; AMD is waiting the maturity of 14XM process(or maybe testing the 14nm FDSOI node that Seronx pointed) to come with the new arch. Until there they realized(finally) they are out of the IPC race and are focusing now to maximize the efficiency of last Bulldozer archs. IMO Basilisk will come as a second Richland with in most part with energetic efficiency improvements.

It takes ~ 5 years to develop a new arch. Keller has been on board since 2012, so we would normally expect a new arch in 2017. Now Keller could have decided to re-architect BD or Husky (depend on where he saw the most opportunity), but I don't think he will have anything 'new' sooner than 2017, given the much smaller CPU development teams (and the fact that AMD added a third uarch with ARM - which is a mind boggling gamble).

Keller did make some comments to Rage3d in 2013:

The best part of interview came in a nice little tidbit about core performance while discussing how much market and application awareness plays a role in core design. Many things are incremental, one of which is legacy performance on new designs. Jim confidently stated AMD are on track to catch up on high performance core, a function of design improvements. We couldn't pin down a timeline for this, but with a time scale of two years core design and one year build and test, it's not going to be immediate. My expectation is 2015.

http://www.rage3d.com/articles/hardware/amd_worldcast/

But clearly Rage3d's interpretation cannot be correct. Carrizo may be the first Big Core CPU to be have some of Keller's influence stamped on it, but I really don't expect anything more dramatic till later on.

 

[mrmt]

Temporary desktop market expansion. A rising tide lifts all boats. Carrizo should be out by the time Win9 is released and will offer plenty of power to the average corporate user.

Carrizzo will be a 28nm design at the time Intel will be selling either cheap 22nm chips for desktops and fielding 14nm chips on the mobile market. AMD die size is already twice the size of comparable Intel processors, that difference will become huge *and* add even bigger gaps in the power consumption front. I'd say that those things might actually worse the trend of smaller market share for AMD, especially with Intel fabs running below their optimum level as they are now.

 

[Ajay]

Carrizzo will be a 28nm design at the time Intel will be selling either cheap 22nm chips for desktops and fielding 14nm chips on the mobile market. AMD die size is already twice the size of comparable Intel processors, that difference will become huge *and* add even bigger gaps in the power consumption front. I'd say that those things might actually worse the trend of smaller market share for AMD, especially with Intel fabs running below their optimum level as they are now.

Well, if Intel actually drops prices a fair amount because of under-utilized fabs then it's pretty much game over AMD anyway. As you've noted yourself, AMD systems are pretty much a value play, take that away and they have nothing left. In fact, if that happens, I don't even see AMD becoming another Via; I see them in bankruptcy court. At that point, they probably won't come out of it as even a shadow of AMD because of their huge debt burden.

 

[Homeles]

IIRC, DDR4 does have better streaming performance - so that would make sense (someone here with a better understanding of DDR4 should correct me if I'm wrong)

Through higher frequencies, yes.

 

[AtenRa]

Well, if Intel actually drops prices a fair amount because of under-utilized fabs then it's pretty much game over AMD anyway. As you've noted yourself, AMD systems are pretty much a value play, take that away and they have nothing left. In fact, if that happens, I don't even see AMD becoming another Via; I see them in bankruptcy court. At that point, they probably won't come out of it as even a shadow of AMD because of their huge debt burden.

Kabini(100mm2) will take the majority of the value market not Kaveri/Carrizo(240mm2). The AM1 platform will be the entry/value/low power, high volume force for AMD in 2014 leaving FM2+ in the higher segment. Same will happen with Intel, ATOM based Celerons and Pentiums will gain volume over entry lever Socket 1150 Celerons/Pentiums.
This is the future for this Desktop segment, and both of them will put more weight in to this segment for Desktop and in Laptop/Tablet the next few years.

 

[Homeles]

But previously you said node shrinks improved performance. So now you're shifting to it lowering power consumption and price instead, because you could not provide any evidence of what you claimed before?

Also, does it really lower price? That assumes it is cheaper for AMD to buy a chip with X billion transistors on 20 nm than on 28 nm from GF/TSMC. I don't think that is the case at the time Carrizo is expected to be released.


Power consumption is not that important on a desktop CPU/APU. On mobile it's another story though.

You've been here since 2010, and you still don't know what new nodes do?

So what can a new process node do? TSMC claims a up to a 30% improvement in performance, or 25% lower power with their 20nm node versus their 28nm node. When was the last time you saw AMD boost their IPC 30%? GloFo claims a 42% increase in performance or a 61% power reduction with 20nm LPM vs 28nm SLP (a testament to the benefits of going gate-last -- TSMC already saw those gains).

High performance CPUs won't fully realize those gains, but mobile does (or gets much closer to it). Mobile is where the money is right now, and that is the main reason why these new nodes are so critical to AMD's success.

But you were talking about desktop, of course. And yes, it's still a big deal there. Remember that 28nm was a crappy node for AMD because AMD dropped SOI. The traditional improvements vs. 32nm bulk where there, but they were hidden by the regression from SOI.

20nm would have been a great node for AMD's desktop processors, because GloFo is moving from the lower-performing gate-first to the higher performing gate-last method. GloFo's not offering a high performance variant, but the same performance boost would apply if they theoretically ported their big cores to TSMC.

 

[Fjodor2001]

You've been here since 2010, and you still don't know what new nodes do?

So what can a new process node do? TSMC claims a up to a 30% improvement in performance, or 25% lower power with their 20nm node versus their 28nm node. When was the last time you saw AMD boost their IPC 30%? GloFo claims a 42% increase in performance or a 61% power reduction with 20nm LPM vs 28nm SLP (a testament to the benefits of going gate-last -- TSMC already saw those gains).

High performance CPUs won't fully realize those gains, but mobile does (or gets much closer to it). Mobile is where the money is right now, and that is the main reason why these new nodes are so critical to AMD's success.

But you were talking about desktop, of course. And yes, it's still a big deal there. Remember that 28nm was a crappy node for AMD because AMD dropped SOI. The traditional improvements vs. 32nm bulk where there, but they were hidden by the regression from SOI.

20nm would have been a great node for AMD's desktop processors, because GloFo is moving from the lower-performing gate-first to the higher performing gate-last method. GloFo's not offering a high performance variant, but the same performance boost would apply if they theoretically ported their big cores to TSMC.

You're rambling, and you don't seem to know what node shrinks do nowadays. 45->22 nm has brought only minor frequency increase for the Intel desktop CPUs. There you have it. The performance improvement has come from uArch changes instead. I.e. node shrinks have not brought the performance improvements.

 

[el etro]

IPC cannot be improved by a die shrinking alone.

IPC cannot be improved by a die shrink.

One way to improve IPC is to making units bigger/more complex, which means that they will need more transistors and consequently they will consume more power.

Reorganization of die space/processor scheme is necessary.
If this was not true, The die size of Haswell and Kaveri cores nowdays would not allow CPU manufacturers to make chips for the consumer market.

 

[Homeles]

You're rambling, and you don't seem to know what node shrinks do nowadays. 45->22 nm has brought only minor frequency increase for the Intel desktop CPUs. There you have it. The performance improvement has come from uArch changes instead. I.e. node shrinks have not brought the performance improvements.

How many times have I been over this, now? 22nm FinFETs had regressed performance at high voltages. At desktop operating voltage, there was next to zero performance benefit, so stock clocks sat still. At higher voltage, there was worse performance, hence the reduced maximum overclocks even when delidded.

This is FinFET-specific. It does not apply to AMD. It is also a one-time hit -- you only go from bulk to planar once. In other words, Intel's 14nm won't have this issue.

Now, let's look at Lynnfield (1156) to Sandy Bridge (1155). A Nehalem i7-870 had a base clock of 2.93 GHz, and a max turbo of 3.6 GHz. A Sandy Bridge i7-2600K had a base clock of 3.4GHz, and a max turbo of 3.8GHz. That's an improvement of 16.0%, and 5.5% respectively.

If we're getting IPC gains of around 10% each generation today, a 10% boost in frequency is nothing to laugh at. As I said before, new nodes are just as important as architecture revisions.

 

[witeken]

You're rambling, and you don't seem to know what node shrinks do nowadays. 45->22 nm has brought only minor frequency increase for the Intel desktop CPUs. There you have it. The performance improvement has come from uArch changes instead. I.e. node shrinks have not brought the performance improvements.

I think he does. Do you know there's something as power consumption, or leakage. Ever heard of Dennard scaling?

The short version is that new nodes have indeed brought sometimes even quite big performance increases, instead of regressions as you'd normally expect below ~90nm.

 

[ElFenix]

How many times have I been over this, now? 22nm FinFETs had regressed performance at high voltages. At desktop operating voltage, there was next to zero performance benefit, so stock clocks sat still. At higher voltage, there was worse performance, hence the reduced maximum overclocks even when delidded.

This is FinFET-specific. It does not apply to AMD. It is also a one-time hit -- you only go from bulk to planar once. In other words, Intel's 14nm won't have this issue.

is intel moving away from FinFETs?

 

[AtenRa]

This is FinFET-specific. It does not apply to AMD. It is also a one-time hit -- you only go from bulk to planar once. In other words, Intel's 14nm won't have this issue.

I dont believe this has to do with FinFet vs Planar, I strongly believe this is made by choice. Intel wanted to have lower power at lower voltages or closer to Threshold(Vt).
And since they(Intel) are continue to pursue lower power consumption we have to expect the same for 14nm.

 

[Fjodor2001]

Do you know there's something as power consumption, or leakage.

We're talking about performance increase through frequency increase on desktop CPUs, and that's something we've not seen much of in the latest node shrinks. Power consumption improvements is something else, and nobody has denied there being improvement in that area.

 

[Homeles]

is intel moving away from FinFETs?

No, there's just a penalty associated with moving to multigate devices. Once you've taken the hit, you can go back to the gains from traditional scaling.

I dont believe this has to do with FinFet vs Planar, I strongly believe this is made by choice. Intel wanted to have lower power at lower voltages or closer to Threshold(Vt).
And since they(Intel) are continue to pursue lower power consumption we have to expect the same for 14nm.

http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_22nm_Device.pdf

Slide 13.

We're talking about performance increase through frequency increase on desktop CPUs, and that's something we've not seen much of in the latest node shrinks. Power consumption improvements is something else, and nobody has denied there being improvement in that area.

These designs are power limited. The clock frequencies these devices reach are a function of power -- at X watts, Y frequency can be achieved.

 

[Vesku]

No, there's just a penalty associated with moving to multigate devices. Once you've taken the hit, you can go back to the gains from traditional scaling.

http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_22nm_Device.pdf

Slide 13.

These designs are power limited. The clock frequencies these devices reach are a function of power -- at X watts, Y frequency can be achieved.

Not sure there will be big jumps in clockspeed with any future nodes without some major breakthroughs in production R&D or a major change in materials. Industry is investing the bulk of node money into efficiency and yields.

 

[Fjodor2001]

These designs are power limited. The clock frequencies these devices reach are a function of power -- at X watts, Y frequency can be achieved.

The problem is that if frequency is increased further, the TDP goes up dramatically on current the latest nodes. So there's really not much headroom for increasing the CPU frequency and paying with some extra TDP.

See what happens to the power consumption when the frequency is increased beyond 3.5 GHz or (3.9 GHz with Turbo):

For reference, the image is created by IDC.

 

[lamedude]

EDRAM is more dense, but as far as I'm aware none of the fabs that AMD has access to has that sort of tech- only IBM and Intel.

TSMC MS and Nintendo use it.