Well Im just putting together information I read on the internet myself...so feel free to show me (reliable) sources that FinFET RIGHT NOW would be more profitable per Wafer than SOI.
Because the reports I find always state that SOI comes out ahead(for now) and some even go as far as claiming that FInFET might actually break Moores law in its current state because of its cost.
I don't think it's worth discussing what you have been reading, but the context of what you have been reading. More specifically, the BUSINESS context of these papers.
What you have been reading is STM PR press blitz in order to sell its SOI process to other foundries, to which you won't find nothing comparable on the FinFET side because nobody is trying to license a FinFET node on the open market as STM does with FDSOI. And STM can't really say otherwise, they have to swear SOI is better than bulk and cherry-pick cases where SOI shines otherwise nobody will buy their product (the node license).
But let's make a sanity check on STM claims:
- Intel moved to finfets in 2012, with 2nd generation finfets in 2014,
- We have on the market TSMC's 28nm since 2011, with their 20nm bulk in 2014.
- Samsung is speeding up its bulk line up, with their finfet node available in 2016.
But What about FDSOI? So far in 2014 we are yet to see 28nm FDSOI in any meaningful application. So despite all the technical advantages you are reading on the web, the IHV aren't knocking the foundries's door to get SOI process and the foundries themselves aren't knocking STM door for licensing deals. Only in the end of 2014 Samsung bothered with it (probably for radio applications) and Globalfoundries... well, they don't count.
More important, why three most important players of the foundry market discarded the technology for their bleeding edge nodes and instead went to FINFET nodes? Because do you think Intel, Samsung and TSMC didn't research SOI before discarding it for their bleeding edge nodes? I think it would be naive to think so.
SOI *could* indeed have some advantages for the business of 2nd and 3rd tier foundry, but even those doesn't seem too keen on SOI, or at least not keen enough to discard FINFETs as an alternative and go SOI-only, but at least for the 1st tier foundries, FINFETs have advantages enough over SOI for them to not even bother with it on their bleeding edge nodes. This is the ultimate metric with we should use to measure SOI against FinFET, not STM press releases.
So far it has been used in research applications.So far in 2014 we are yet to see 28nm FDSOI in any meaningful application.
Lets not forget the ST-Ericson NovaThor L8580 w/ Two Cortex-A9 Cores @ 3 GHz. I'm currently looking for the spiritual successor of this ASIC.Experimental results in Figure 10 (OpenSPARC T1 at 28nm
FDSOI technology) show energy comparison with different process
variations between resilient designs and conventional ones. In the
figure, small, medium and large margins respectively indicate 1σ,
2σ and 3σ for SS corner. Note that resilient designs are signed
off at typical case; while conventional ones use worst-case signoff.
Results show that an optimized resilient design can achieve up
to 10% energy reduction compared to that from a brute-force
implementation where error-tolerant flip-flops are simply applied
to the most timing-critical paths. Up to 20% energy reduction is
achieved in resilient designs as compared to conventional pure-
margin designs. The results also show that with larger process
variation, resilient designs with brute-force implementation have
larger energy cost mainly due to throughput degradation (e.g., FPU
and EXU), while the optimized designs are able to jointly minimize
the number of error-tolerant flip-flops and error rate, thus achieving
greater improvement over brute-force. In addition, the additional
circuits for error detection typically cause large area overhead
in resilient designs. This example also shows that an optimized
implementation is able to significantly reduce such area overhead
(e.g., by an average of 45%).
Now, the checklist is I am looking for 13+ more designs to fit into the 21+ tape-outs.
Also, have to watch out for the first 14nm win.
SMT said:http://seekingalpha.com/article/262...-results-earnings-call-transcript?part=single
So first, okay, to address our consumer product portfolio, 28 of FD-SOI and the next-generation worldwide choice for all this kind of business. And we have to look at all implication for the advanced part of our technology roadmap related to the 2 points I mentioned to you. And we have start to review an assessments to position our sales material element.
Carlo Bozotti - Chairman of Management Board, Chief Executive Officer and President
And I think I can conclude that the -- so this is new for us. It's something that recently been announced. And at this point, I think all options are open.
Kai Korschelt - BofA Merrill Lynch, Research Division
So could I -- just to clarify. So you're saying that FD-SOI at 20-nanometer -- 28 nanometers could be a 1 or 2 nodes sort of product event? But for further nodes, you may sort of keep all options open, including not developing that technology further? Is that right?
Carlo Bozotti - Chairman of Management Board, Chief Executive Officer and President
Yes, on the FD, it's right, it's clear. We have 2 nodes. This is very, very important for ST, for our customers is fully committed that we have a lot of awards. And so this is the 28 and, let's say, the 14 or whatever generation so that this node -- this is absolutely important for ST. What we said that we are reviewing the activity for the part of nodes, and this is following a very recent announcement. And today, all options are open.
(...)
And many parts of the semiconductor market will remain for a long time on 28 and 14-nanometer on FD-SOI or on some FinFET when the FinFET will be ready. So this is exactly what we think today.
CEA-Leti partnered up with STM to do the baseline 28nm FDSOI.So, there you have it. STM has 28nm, and "something" 14nm, but they do not have a 10nm yet and aren't committed to build it yet, let alone a 7nm.
http://i.imgur.com/yrzjA0v.jpg*However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.
There is no reason for AMD to stay on 28nm for Carrizo/Carrizo-L, unless it is for FDSOI. They are required to tapeout designs on a [redacted] node from GlobalFoundries. The FDSOI roadmap to production would also allow AMD to be on time for node switches. GloFo's 20nm LPM has been in volume since 2013, TSMC's 20nm SOC has been in volume since Q2 2014.i thought that this thread was about Carrizo.
There is no reason for AMD to stay on 28nm for Carrizo/Carrizo-L, unless it is for FDSOI.
In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum).
Was a slight mention in a few articles much like 28nm SHP.Another foundry competitor, GlobalFoundries, is supporting three options: bulk CMOS, FD-SOI and SSRW.
28nm SHP is part of the "Normal" set of nodes.Edit: Kaveri was on SHP if I dug that out correctly? Still...what are the differences?
Haven't heard about SSRW... and I've been into this for at least 4 years now. Doesn't look terribly interesting, though, from the looks of it.Sorry, for the double post/revival.
Carrizo and Carrizo-L will be on GlobalFoundries' 28nm SSRW bulk node.
Was a slight mention in a few articles much like 28nm SHP.
I could not find any Carrizo benchmarks in the article.
How did you arrive at that conclusion? I could not find any Carrizo benchmarks in the article.
In market by mid year might mean its being sampled now and shipped to system builders through the first quarter for a mid year consumer market release
So...Carrizo systems will basically be competing with the tail end of Broadwell/beginning of Skylake at this point.
If they ever ship at all. Still waiting for someone to ship the Discovery tablet concept. You know, the one that got benchmarked by Anandtech, then never saw the light of day.
http://www.anandtech.com/show/7974/...tecture-a10-micro-6700t-performance-preview/3
I dont get why AMD doesnt just do a 1st party laptop/tablet a la nvidia and/or intel. They are just dying from the lack of products in the market!
You mean skylake will launch in second half of this year ? It'll launch (full fledged) sometime during first half of next year with paper launch around the holiday season of 2015, just like Broadwell. There is no way Intel will cannibalize their own stock of Broadwell anytime before Skylake launches, I think there was some recent news that it's launch has been delayed further till the end of this year ~So...Carrizo systems will basically be competing with the tail end of Broadwell/beginning of Skylake at this point.
Of course the CPU is tiny: 2x smaller than its predecessor. It simply as big as it needs to be to be a high-end CPU (architecture) with good power consumption.
You mean skylake will launch in second half of this year ? It'll launch (full fledged) sometime during first half of next year with paper launch around the holiday season of 2015, just like Broadwell. There is no way Intel will cannibalize their own stock of Broadwell anytime before Skylake launches, I think there was some recent news that it's launch has been delayed further till the end of this year ~
http://wccftech.com/intels-6th-gene...spring-15-updates-2015-2016-mobility-roadmap/
http://wccftech.com/intel-skylake-s-delayed-september-ctober-2015/
Also this ~