[Anandtech] Intel's Architecture Day 2018

[PeterScott]

Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86

I know some bits of this were getting some mention in other threads, but it seems like it was big enough to warrant it's own discussion.

Highlights for me were a new architecture (finally) Sunny cove, that looks to have potential (4-5 wide allocation) to deliver Intels first real IPC improvement in MANY years, and also what should be a nice improvement in the the IGP, and a look at Intels multichip solutions(Foveros) and Intel Big-little.

The Q&A was also somewhat interesting, like where they admit being node-locked on their designs really messed them up, and they will be more node agnostic in the future.

Overall, more actual news than we have seen from Intel in some time.

 

[DrMrLordX]

Sapphire Rapids contains one of the new cores Intel is working on (according to the CanardPC guy, it's actually Golden Cove based). But my point is that you are comparing a product/SoC level thing with individual cores. It's not apples-to-apples.

Put another way, if I said: "I'm not really interested in Zen, but I am looking forward to Rome," that's not really an apples-to-apples. The right comparisons would be, "I'm not really interested in Zen, but I'm looking forward to Zen 2" or "I'm not really interested in Naples, but I'm looking forward to Rome."

I know what you are trying to say, but I don't think you fully grasp what I am saying here.

Now, maybe Intel isn't going to go with a radical redesign for Sapphire Rapids if all it is is Golden Cove wrapped up in a server-first package. In that case it's just, you know, more x86, on a platform that consumers wouldn't want anyway. Probably.

But what if Intel went with something as wildly different as IA64 was back when there were the first whispers of Itanium? That would be groundbreaking, earth-shattering. It would have implications for Intel's entire CPU lineup (potentially). Zen vs Zen2? No. Not even in the same ballpark.

Someday, Intel is going to have to get away from Core. Period. Sunny Cove and Willow Cove are not that. We are in a period of flux where no one - not even Intel - is entirely beholden to the backwards compatibility monster. ARM is making a push into several traditionally x86 markets. Intel could roll out a non-x86 design just as easily. If they're going "server only" then it could be Itanium all over again. For Intel's sake, it really ought to work this time. Unlike Itanic.

I want to see if Intel has the chops to try something that bold. That's all.

 

[Yotsugi]

But what if Intel went with something as wildly different as IA64 was back when there were the first whispers of Itanium?

You know well enough how that trainwreck ended.

Someday, Intel is going to have to get away from Core.

Moving from complex OoO machine to exactly WHAT?

Intel could roll out a non-x86 design just as easily.

Why would a different ISA make, eww, any difference?
As long as it's still complex OoO machine.

I want to see if Intel has the chops to try something that bold. That's all.

The age of bold is far and away gone.

 

[Arachnotronic]

You know well enough how that trainwreck ended.

Moving from complex OoO machine to exactly WHAT?

Why would a different ISA make, eww, any difference?
As long as it's still complex OoO machine.

The age of bold is far and away gone.

This. Just so much this.

 

[moinmoin]

A couple years ago when I asked when one could expect significant changes to the x86 core itself by Intel instead further expanded SIMD/AVX capability I was referred to Sapphire Rapids. So I can see how expectations for this grew ever further since.

 

[Yotsugi]

A couple years ago when I asked when one could expect significant changes to the x86 core itself by Intel instead further expanded SIMD/AVX capability I was referred to Sapphire Rapids. So I can see how expectations for this grew ever further since.

Haswell was already that, and was decent.
What Intel needs is a new SoC methodology to scale up the core counts without resorting to XBAWKSUEG dies with mid-double digit yields tops.

 

[moinmoin]

Haswell was already that, and was decent.

Decent is the right word. And it was over 5 years ago.

XBAWKSUEG

Sorry?

 

[Yotsugi]

Decent is the right word. And it was over 5 years ago.

Not my fault Intel haven't decoupled their cores from process IP.
ICL was a 2017 product, back then during the dark times.

Sorry?

Huge.

 

[moinmoin]

Not my fault Intel haven't decoupled their cores from process IP.

That's why we are waiting for Sapphire Rapids...

Huge.

That much I also understood.

 

[Yotsugi]

That's why we are waiting for Sapphire Rapids...

I mean, it's just an ICL successor.
It's gonna fight Milan+1 so good luck to ppl at Intel.

 

[moinmoin]

I mean, it's just an ICL successor.
It's gonna fight Milan+1 so good luck to ppl at Intel.

Yeah...
One would think the chip design staff did anything significant while the foundry staff was stuck working on non-working nodes. But if the generational staccato of features is the same just without the tick tock now we are looking an tiny changes relative to the passage of time.

 

[jpiniero]

Haswell was already that, and was decent.
What Intel needs is a new SoC methodology to scale up the core counts without resorting to XBAWKSUEG dies with mid-double digit yields tops.

That's what Fovoros is. The Intel patent related to it had CPU dies stacked on top of a die which had the Mesh+L3. Might be a while before you see it used in a server product though.

 

[Yotsugi]

That's what Fovoros is.

Yikes.
TSVs tend to absolutely murder yields.
So no.
SPR uses EMIB anyway, that's multi-terabit b/w per bridge so should be fun anyway.

 

[jpiniero]

Yikes.
TSVs tend to absolutely murder yields.
So no.
SPR uses EMIB anyway, that's multi-terabit b/w per bridge so should be fun anyway.

Cooper Lake might be using it; but it's still two giant dies. The question with EMIB is how you would get from one die to another if they were not directly connected (ie: lots of dies).

 

[Yotsugi]

Cooper Lake might be using it; but it's still two giant dies. The question with EMIB is how you would get from one die to another if they were not directly connected (ie: lots of dies).

CPL doesn't use EMIB and multiple hops!

 

[krumme]

Guys. We all missed the big news here.

What will the decoupling of process do for how Intel is working in the future?

There is solid reasons to tie design to process. Especially at the size of Intel. Look at prior history and we know why. You simply get nearer a 100% optimal product. Stunning cache performance what not.

Imo this change is primarily NOT to safeguard, as Intel have reasources to safeguard running more parallel teams, but in a broader sense to work as a foundry partner.

The days of keeping your process to yourself is over. The cost outweight the benefits.

This is the news here.

Intel have for years been skitzofrenic if they were a process or design company. Now they will have those more separated and independent.

And damn. Its good to see the old Intel. Open and enthusiastic. Hiring Keller and Raja is the best that could happen to them. Raja is darn strong on the visions where Intel lacked and he brings tons of wit and humour. It is always a pleasure to hear Raja and Keller talk. Fantastic Intelects. Intel was in dire need of such personalities. Hope they can shake up things a bit and inspire for even more.

The numbers looks very good now but It will be rough the next 3 years or so but then things will hopefully lighten up. Intel is in a transition process. I am sure zen2 and 3 will smoke whatever Intel can scramble for the next years but they will be back.
Good times.

 

[moinmoin]

The days of keeping your process to yourself is over. The cost outweight the benefits.

This is the news here.

It seems you missed the news that Intel's Custom Foundy efforts are no more.

 

[Yotsugi]

It seems you missed the news that Intel's Custom Foundy efforts are no more.

Not official yet, also did they ever land any major customers?

 

[Dayman1225]

Not official yet, also did they ever land any major customers?

No

 

[NTMBK]

Not official yet, also did they ever land any major customers?

They landed LG's SoC business, which ended so well for LG.

 

[PotatoWithEarsOnSide]

A 3-5s benchmark is only ever testing turbo capabilities, and is certainly not representative of real world performance.

 

[DrMrLordX]

You know well enough how that trainwreck ended.

VLIW didn't work in its intended application, and the implementation was also bad. Didn't mean something non-x86 had to end that way. Look at what Apple is doing with ARM right now. Are you saying it was impossible for Intel to do that?

Moving from complex OoO machine to exactly WHAT?

Push comes to shove, they go ARM or RISC-V, assuming they can't dream up something better.

Why would a different ISA make, eww, any difference?
As long as it's still complex OoO machine.

See above.

The age of bold is far and away gone.

If they cling to Core, they will slowly circle the drain.

 

[Yotsugi]

Push comes to shove, they go ARM or RISC-V, assuming they can't dream up something better.

They don't need either.
ISA doesn't matter since 1995.
rv64 also currently blows for HP designs.

If they cling to Core, they will slowly circle the drain.

Iterations are a thing.

 

[DrMrLordX]

Iterations are a thing.

Tell you what. Watch Apple's design team walk all over them, and AMD. Then get back to me. They're iterating, alright . . .

 

[Arachnotronic]

Tell you what. Watch Apple's design team walk all over them, and AMD. Then get back to me. They're iterating, alright . . .

So AMD iterating on Zen is great, but Intel building better cores over time is going to get them "walked over"? OK.

 

[Yotsugi]

So AMD iterating on Zen is great, but Intel building better cores over time is going to get them "walked over"? OK.

Good ole' double standards.
Tbf Intel's execution in their core biz these past few years has been less than desirable and that's saying it lightly.