Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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[soresu]

Rumour: Apple M5 will be on TSMC 3nm

Apple Orders M5 Chips From TSMC Ahead of Late 2025 Production

Apple has ordered M5 chips from TSMC as the company begins production development of its next-generation processor for future devices, reports...

www.macrumors.com

Very possibly true given first gen N2 won't have back side power delivery.

Consequently moving straight to N2P from N3 were provide a serious uptick in perf/watt.

 

[RTX]

Rumour: Apple M5 will be on TSMC 3nm

Apple Orders M5 Chips From TSMC Ahead of Late 2025 Production

Apple has ordered M5 chips from TSMC as the company begins production development of its next-generation processor for future devices, reports...

www.macrumors.com

https://www.taiwannews.com.tw/news/4949531

It'll be N3 because N2 starts production in late 2025 which means they won't have products on shelves until at least June 2026.

 

[DrMrLordX]

It'll be N3 because N2 starts production in late 2025 which means they won't have products on shelves until at least June 2026.

So N3P?

 

[jdubs03]

So N3P?

Yea it’ll be N3P.

 

[FlameTail]

M3 (2023) = N3B
M4 (2024) = N3E
M5 (2025) = N3P

3 consecutive generations of M chips using the same node family (TSMC 3nm).

Really shows how Moore's Law has slowed down.

 

[The Hardcard]

M3 (2023) = N3B
M4 (2024) = N3E
M5 (2025) = N3P

3 consecutive generations of M chips using the same node family (TSMC 3nm).

Really shows how Moore's Law has slowed down.

Things are just different now, Moore’s Law has been a loose concept for years. Node families are part of that. It used to be just nodes. There was no 130 nm node family, it was just a 130 nm node. Then a 90 nm node.

It part of why there is so much contention and confusion over current node names anyway. Things are just different than when Gordon Moore was active.

Even the the last planar nodes were becoming an issue, but things became really different with FinFETs. That was a major advancement, but it really severed the connection between node names and gate length or any other specific measurement of transistors.

Things are different than Moore’s Law, yet advancements continue, even within node families.

 

[igor_kavinski]

Really shows how Moore's Law has slowed down.

No, it shows how incompetent Intel became. TSMC does not care about Moore's Law.

 

[johnsonwax]

No, it shows how incompetent Intel became. TSMC does not care about Moore's Law.

I don't think either is correct. Moore's law is just a localized snapshot the larger law of accelerating returns. But the larger law doesn't care that the technological pace come from a specific technology - we can compensate for slowing single core compute by a shift to multi-threaded, multi-core compute but we can also compensate by cloud/distributed compute and by a mess of other things - such as an inflection point in the cost of electricity that just allows us to run more compute. Hell, the invention of calculus is part of the law. It really doesn't care how it comes about. So I don't think Moore's law is a law, but a local observation of how the broader law of accelerating returns maps onto the semiconductor market, and people in the market can't see outside of it to recognize that the compute gains might come from somewhere completely different.

And where the law of accelerating returns has baked into it the economic realities around that (because it allows for the catalyst to be economics), Moores law does not. I don't think we've hit a point where the technology to increase transistor density is lacking, I think we've hit a point that it's either become too expensive, or we've structured the system in such a way that we cannot bring the money to the problem. Consolidation in the market is one way this can happen, monopsonies is another way it can happen. Finance alone can cause it to happen independently of the other two, etc. For instance, an invasion of Taiwan will guarantee that for a short period of time because of all of the above.

And I should note, it's not up to TSMC to care about it or not in the same way it's not up to you to care about gravity or not. Laws apply to you whether you like it or not.

 

[igor_kavinski]

And I should note, it's not up to TSMC to care about it or not in the same way it's not up to you to care about gravity or not. Laws apply to you whether you like it or not.

TSMC doesn't owe Moore anything so they don't need to respect his law whether it applies to them or not and they don't try to pretend that they are forging ahead with new process advancements just to pay homage to some dude who himself called his law a "wild extrapolation". Intel, on the other hand, supposedly reveres Moore to the point that they proclaimed "In Moore we trust!" but then failed to live up to it with their prolonged 10 nm debacle and general managerial incompetence of Krzanich. But thanks for your thoughts on the law itself. Interesting.

 

[johnsonwax]

TSMC doesn't owe Moore anything so they don't need to respect his law whether it applies to them or not and they don't try to pretend that they are forging ahead with new process advancements just to pay homage to some dude who himself called his law a "wild extrapolation". Intel, on the other hand, supposedly reveres Moore to the point that they proclaimed "In Moore we trust!" but then failed to live up to it with their prolonged 10 nm debacle and general managerial incompetence of Krzanich. But thanks for your thoughts on the law itself. Interesting.

You have a very strange understanding of what 'laws' are.

 

[poke01]

Treat semi conductor laws the same as you would treat Math laws. They apply to everyone.

 

[misuspita]

Moore's "law" is an observation of an economic fenomenon, which in a limited period of time was possible, not a physical law.

 

[Doug S]

Very possibly true given first gen N2 won't have back side power delivery.

Consequently moving straight to N2P from N3 were provide a serious uptick in perf/watt.

Who says N2P will have it either? I think it is likely that just as N2/A16 are the same process without/with BSPDN that N2P/N14 might be the same process without/with BSPDN.

If TSMC is steering mobile away from BSPDN due to heat issues, until those issues are ameliorated Apple may not want it even for Apple Silicon given the importance they place on lower power, fanless or as quiet as fanless devices, etc.

 

[name99]

If TSMC is steering mobile away from BSPDN due to heat issues, until those issues are ameliorated Apple may not want it even for Apple Silicon given the importance they place on lower power, fanless or as quiet as fanless devices, etc.

Who's claiming that BSPDN has heat issues, especially at mobile power levels? The claim makes no sense technically.

 

[Doug S]

Who's claiming that BSPDN has heat issues, especially at mobile power levels? The claim makes no sense technically.

TSMC is, apparently. With the transistors sandwiched between multiple oxide layers on both sides apparently getting the heat out of the chip is more of an issue than when the transistors were on the bottom (top when socketed) with only silicon in the way.

The people here who know the technical details of how the chips are made support that assessment and I don't have the knowledge base to argue with them, even though I don't understand the physics of that given how thin the oxide layers are.

 

[FlameTail]

	9950X	M4 Max
Geekbench 6 ST	3500	4000	+15%
Cinebench 2024 ST	150	180	+20%

Apple has a bigger lead in Cinebench than in Geekbench over AMD. How can that be? I was told that Geekbench favours ARM CPUs because it uses extensions such as SME to 'inflate' the score.

Is Cinebench also now getting a paycheck from Apple?

/s

 

[poke01]

	9950X	M4 Max
Geekbench 6 ST	3500	4000	+15%
Cinebench 2024 ST	150	180	+20%

Apple has a bigger lead in Cinebench than in Geekbench over AMD. How can that be? I was told that Geekbench favours ARM CPUs because it uses extensions such as SME to 'inflate' the score.

Is Cinebench also now getting a paycheck from Apple?

/s

Cinebench 2024 is an RT test, and Apples cores are really good at ray tracing. You can see the blender test here.



This is without SMT too and under 65 watts for the CPU package.

 

[FlameTail]

Looking at the Single Core Ray Tracer subtest in Geekbench 6, the M4 Max is only 10% faster than 9950X.

ASRock X870E Taichi Lite vs Mac16,5 - Geekbench

Does Geekbench Ray Tracer test not take advantage of the full capability of the core?

 

[FlameTail]

M4 Max
Cinebench 2024
~2100 points at 65W.

The competition meanwhile;

 

[poke01]

The competition meanwhile;

We need to wait for 285HX but goodbye battery life..

 

[MS_AT]

Does Geekbench Ray Tracer test not take advantage of the full capability of the core?

It could always be the other way around. That Cinebench is not making full use of modern x64 cores.

We need to wait for 285HX but goodbye battery life..

There is still Strix Halo, probably it will be at least able to compete with M4 Max laptops on price (the higher one wins? ) but will suffer from usual AMD availability...

 

[okoroezenwa]

It could always be the other way around. That Cinebench is not making full use of modern x64 cores.

That would be a hilarious turn of events.

 

[The Hardcard]

Looking at the Single Core Ray Tracer subtest in Geekbench 6, the M4 Max is only 10% faster than 9950X.

ASRock X870E Taichi Lite vs Mac16,5 - Geekbench

Does Geekbench Ray Tracer test not take advantage of the full capability of the core?

The question is why different code working on different data doesn’t make the exact same lockstep difference on 2 architectures?

The difference between 10, 15, and 20 percent is not night and day. I would think the opposite. If multiple codebases written by separate individuals or groups all ended up exactly 18 percent faster one processor, that’s when I am wondering about manipulation and payoffs.

If there was one true precise performance ratio, then only one true benchmark would be necessary. This difference just shows why using multiple benchmarks and tests is the only way to get the whole picture.

 

[FlameTail]

It could always be the other way around. That Cinebench is not making full use of modern x64 cores.

Even X Elite is undeperforming in Cinebench relative to Apple CPUs, so I don't think that's the case.

	Geekbench 6	Cinebench 2024
M3	3200	148
M4	4000	184
X Elite	3200 (Linux)	133

 

[poke01]

Even X Elite is undeperforming in Cinebench relative to Apple CPUs, so I don't think that's the case.

	Geekbench 6	Cinebench 2024
M3	3200	148
M4	4000	184
X Elite	3200 (Linux)	133

You have to look at the Ray tracer sub test. In any case the Geekbench RT tests line up with Cinebench give or take

I