Apple XServe - rackmount server

[AndyTriboletti]

wicked cool--anyone want to spot me 3k?

 

[bizmark]

Originally posted by: Eug


Errr.... Huh? I hope you guys don't believe that your system bus is truly running at 400 MHz or 266 MHz or whatever.

Well, I know MINE isn't, since I've got a Celeron

But what do you mean? I mean, I guess it depends on the definition of 'system bus'. With modern systems, the 'north' bus (RAM/AGP) is 266/whatever, while the 'south' bus (PCI and I/O) is still umm I don't know, like 100 or 133? So what does Apple man by the 'system bus'? Surely if they have DDR, then the memory-to-CPU pipe, whatever they want to call it, runs at 266... right?

edit: OIC. N/M then.

 

[RanDum72]

The DDR SDRAM in that is meaningless, seeing as how the system bus is only 133MHz.

PC2100 DDR actually runs at 133mhz, because of the 'doubling' effect of DDR, people usually says the FSB is 266mhz. But it is actually 133.

 

[Daovonnaex]

Originally posted by: Eug

Originally posted by: bizmark

Originally posted by: Daovonnaex
The DDR SDRAM in that is meaningless, seeing as how the system bus is only 133MHz.

Woah! I didn't notice that. That's stupid!

Errr.... Huh? I hope you guys don't believe that your system bus is truly running at 400 MHz or 266 MHz or whatever.

The difference is that in the case of an Athlon, the system bus is capable of transmitting two data cycles per clock, as opposed to the current Apple platform, which is only capable of sending one.

 

[TheWart]

What I want to know is when is Anand going to be using these to power the forums?

 

[AGodspeed]

In very laymen terms, due to the fact that the Athlon utilizes a double pumped (i.e. DDR) Front Side Bus, it is able to effectively make use of DDR memory modules.

Motorola's G4 processors on the other hand do not have any such DDR Front Side Bus as the Athlon does (and if you're wondering, the PIII Tualatin and Celeron don't have a DDR Front Side Bus). Therefore, there's no real point in using DDR memory modules with a G4-powered (or PIII-powered) system, it simply won't be able to use the extra bandwidth that DDR memory modules bring over PC133 modules.

 

[Sunner]

For a good example of a waste of good DDR SDRAM, look at VIA's Apollo 266 chipsets for the Tualatins, no performance difference over the Apollo133 series.

Anyways, that server looks nice, not Apple cute like the regular Macs, but actually rather clean and stylish.
Me likes, though I couldn't really care, heck it's a server, assuming they work right, the admin's shouldn't have to look at them too often

 

[Nemesis77]

Nice rack !

 

[Thor86]

Oooh the pcb is blue - mac user.

 

[Eug]

The difference is that in the case of an Athlon, the system bus is capable of transmitting two data cycles per clock, as opposed to the current Apple platform, which is only capable of sending one.

OK. I stand corrected.

In very laymen terms, due to the fact that the Athlon utilizes a double pumped (i.e. DDR) Front Side Bus, it is able to effectively make use of DDR memory modules.

Motorola's G4 processors on the other hand do not have any such DDR Front Side Bus as the Athlon does (and if you're wondering, the PIII Tualatin and Celeron don't have a DDR Front Side Bus). Therefore, there's no real point in using DDR memory modules with a G4-powered (or PIII-powered) system, it simply won't be able to use the extra bandwidth that DDR memory modules bring over PC133 modules.

OK, and that would explain the rather limited bandwidth Apple claims with their servers. I was under the impression that new variants of the G4's were going to be capable of utilizing extra bandwidth, and hence the justification for the design. However, further reading suggests that this is not the case with the G4 that is actually used in the current Xserve. I guess that was just incorrect speculation. See this diagram for a cartoon of the Xserve architecture.

However, can't other components via DMA utilize the extra bandwidth, even if the CPU cannot? Isn't there a PIII chipset somewhere that allows utilization of DDR (albeit with only minor performance boosts)? In the case of this server, wouldn't that boost still be significant (although not huge)?

 

[Eug]

Originally posted by: Eug
I was under the impression that new variants of the G4's were going to be capable of utilizing extra bandwidth, and hence the justification for the design. However, further reading suggests that this is not the case with the G4 that is actually used in the current Xserve. I guess that was just incorrect speculation.

OK, more "info" from The Register here. Only newer G4 7470 chips, which are not yet in production, will support a true double-pumped FSB supporting 266 MHz DDR. The 7455 is what is used in the Xserve. Apple has not announced support for the 7470 however.

And I wonder if the 7500 is even in the radar yet...

 

[Eug]

BadAndy speaks....






...too bad he's over my head.

 

[neuralfx]

hm well .. ok "wow" it looks coool .. which it does, i'll give you that .. but how bout some benchmarks before we all drool too much eh =)?
-neural

 

[BFG10K]

How can anyone in their right mind take this piece of crap seriously? I mean come on, Intel's RAM that they use on desktops is faster than Apple's top server CPUs. If that isn't a joke I don't know what is.

isn't the 266 the fsb?

Heck no. That piece of crap is still on a 133 MHz FSB/133 MHz SDR. I don't know were they dreamed up the 266 MB/sec garbage but you can bet it'll come from something as worthless and meaningless as peak GFLOPS.

 

[Sunner]

There there BFG, take it easy or you're gonna burst a bloodvessel

 

[Yoshi]

I think it's great Apple has relaeased a server class system. Apple's has a serious advantage over Intel and AMD in the server marketplace. RISC architecture along with a Unix OS, hmm I smell a winner here. I would take that any day over an Intel/Microsoft platform.

I'm a long time PC user who recently got into Mac's buying a Powerbook laptop and a G4 933Mhz tower. Apple's hardware is great to begin with, add Apples OS X Unix OS to that and my PC can take a hike. Seriously, I still use my PC but a lot less than I used to and I'm more than impressed with Apple's latest offerings.

 

[Charles]

Would Anand buy it for his webserver?

 

[Eug]

Originally posted by: BFG10K
How can anyone in their right mind take this piece of crap seriously? I mean come on, Intel's RAM that they use on desktops is faster than Apple's top server CPUs. If that isn't a joke I don't know what is.

I don't know too much about the server market but it may be of interest for you to take a look at Dell's PowerEdge 1650 servers, which are about in the same class and price range. Intel Pentium III's with SDR SDRAM. Even their $8300 PowerEdge 2550 servers use Pentium III's (single CPU) with SDRAM.

EDIT:

What does this mean (from BadAndy)?

It is absolutely obvious that none of you have ever engineered for the bus or know what you are talking about -- you are just pulling (often outdated) Moto sheets off the web, reading the synopsis, and then putting up drivel but in a fog-horn voice.

The 133 Mhz isn't a _limit_ it is a _guarantee_ ... and it applies to individual single-address-tenure transactions. A neglible fraction of the CPU traffic are single-beat transactions ... when you go through the timing diagram for the '55 for 4-beat (cache-line) transactions, and if you assume that there aren't legacy-crap on the FSB... you can go a lot faster, particularly assuming Advance Bus Grant is asserted. In a single CPU system you can just tie this line always asserted. In a MP system you can't, but external advance arbitration logic (which you can fold into the northbridge) can get this early-out with respect to an access cycle for each CPU ... with the price of a 1 bus-cycle increase in latency for bus-grant request/grant ... and to get DDR this price would be REALLY minimal in overall impact.

Go read the timing state diagrams for the '55 ... carefully. Then read all the errata ... carefully. Then presume that the errata are in the process of being fixed. Go into the lab and play around with a '55 and a bus-analyzer. Lots of folks have.

Also assume that the folks doing the PCB layout aren't utter twits and that the FSB traces are short, well terminated, and not anywhere near close to Moto's worst-case performance assumptions (which are very conservative and assume that the FSB is fanning out to all sorts of legacy crap.)

My guess is that you will see these servers posting combined CPU bandwidths above 1 Ghz the day they roll out, and with tweakage on various fronts and revs of the CPUs and northbridge (which may be incremental) the FSB bandwidth will close in on the DDR bandwidth.

The CPUs can ALREADY handle one FSB memory transaction every other CPU cycle maximum (this has been true for a long time) 2 x 266 Mhz = 533 Mhz. This is NOT any sort of limiting issue.

There are many facets of the BFish ignorance here, but among them one of the most egregious is the belief that the achieved FSB performance is an INTEGER ratio of some frequency. (Implying that it is going to be 133 Mwords/sec or 266 Mwords/sec, and nothing in between) This wasn't the way the x86 world scaled its way to DDR, and it isn't going to be how the MP G4+ will either.

What is odd though is that the first DDR system Apple is bringing out is MP. Think about that.

 

[kgraeme]

Some announcements related to the XServe:

• Oracle is bringing Oracle9i Database and Oracle9i Real Application
  Clusters to Mac OS X Server
• HP is bringing OpenView management software to Mac OS X/Mac OS X
  Server

 

[cmdrdredd]

the cache on the g4 CPU is the DDR not the memory!

 

[thanared]

Originally posted by: Daovonnaex
The DDR SDRAM in that is meaningless, seeing as how the system bus is only 133MHz.

I think it's beautiful myself. But don't over look what appro has produced in 1u's. I have a dual athlon appro and it too is beautiful.

Another thing you need to look at is the fact that P3 xeon servers are still very popular in Compaq, HP, Dell, etc... product line.

Notice that 8 way systems use Intel's Profusion. For you lazy folks.. it says this concerning memory:

"The Profusion chipset architecture is a hybrid of dual-ported memory and switch-based shared memory multiprocessing architectures, optimized for systems with eight processors. The three-bus, balanced architecture overcomes bottlenecks in both the memory system and I/O channels, making improved performance possible, through increases in both burst and aggregate bandwidth. Specific features of the chipset include:

[*]Dual 100MHz processor buses and dedicated 100MHz I/O bus.
[*]Dual interleaved SDRAM memory controllers, supporting up to 32GB of SDRAM, dual cache-coherency filters.
[*]Adherence to Intel's MPS 1.4 specification for interoperability with major operating systems, including Microsoft* Windows NT* and Windows* 2000 and several versions of UNIX*. "

Maybe someone out there with some knowledge can lend a hand here. Are we to believe that those eight processors share 2 100 MHz busses to the memory? That would be 1.6 gigbytes/sec... Lower than PC2100 and lower than RDRAM in the P4.

Should this tell us something about memory and servers? Or is the 8 way Intel chipset crap?

 

[n0cmonkey]

Originally posted by: cmdrdredd
the cache on the g4 CPU is the DDR not the memory!

Double Data Rate (DDR) memory: Xserve has four DIMM slots that take industry-standard PC2100 DDR SDRAM memory. This high-speed memory handles two memory operations per clock cycle for a 266MHz data rate ? a blistering 2.1GB/s throughput that?s twice that of the Single Data Rate (SDR) memory used in other servers in this range. Memory capacity is scalable up to 2GB, letting you scale up your server memory to run RAM-hungry applications simultaneously, and to accommodate sharp spikes in demand.


From here

 

[BFG10K]

Dell's PowerEdge 1650 servers, which are about in the same class and price range. Intel Pentium III's with SDR SDRAM. Even their $8300 PowerEdge 2550 servers use Pentium III's (single CPU) with SDRAM.

That's true but these systems aren't the best servers available in the PC world. A dual Xeon/Palomino server will absolutely cane Apple's machine, a machine that is Apple's best.

 

[n0cmonkey]

Originally posted by: BFG10K

Dell's PowerEdge 1650 servers, which are about in the same class and price range. Intel Pentium III's with SDR SDRAM. Even their $8300 PowerEdge 2550 servers use Pentium III's (single CPU) with SDRAM.

That's true but these systems aren't the best servers available in the PC world. A dual Xeon/Palomino server will absolutely cane Apple's machine, a machine that is Apple's best.

Its their first entry into the rackmount market, give them some time. Also, from reading some of the posts in the ars forum, it looks like there are plenty of new things in the works.

 

[ElFenix]

the fact that they aren't charging individual user licenses for their unix o/s will sell them a ton of systems.