Flexible FPU (flexible floating point Unit): 1 for each modual (has its own scheduler), a extensions called AVX, can handle 256-bit FP execution. Single precision commands are 32-bit and double precision are 64-bit. With today’s standard 128-bit FPUs, you execute four single precision commands or two double precision commands in parallel per cycle. With AVX you can double that, executing eight 32-bit commands or four 64-bit commands per cycle.
"The beauty of the Flex FP is that it is a single 256-bit FPU that is shared by two integer cores. With each cycle, either core can operate on 256 bits of parallel data via two 128-bit instructions or one 256-bit instruction, OR each of the integer cores can execute 128-bit commands simultaneously."
Flex FPU makes bulldozer a floating point monster.
Approximately 116% performance improvement per core; of course this doesn't take clock speed into account so it's likely somewhat less considering clock per clock per core.
Not bad, if it's true, of course.
That is about right since AXV can almost double performance. We are seeing similar (80%-100%) improvements in SB with AVX FP tests.
Given that, napkin math suggests the alleged Bulldozer CPU has a clock speed around 3 GHz to 3.5 GHz.
That won't happen with Bulldozer, as using AVX effectively halves the number of FPUs.That is about right since AXV can almost double performance. We are seeing similar (80%-100%) improvements in SB with AVX FP tests.
That won't happen with Bulldozer, as using AVX effectively halves the number of FPUs.
I belive the point of this thread is just that.... AMD floating point performance exploded with the bulldozer, compaired to their older cpus.
It did? Here I thought that for anything that doesn't make use of the new FMAD, FP performance was effectively halved per 'core' since it's the exact same FP resources as a Phenom II now shared between two integer cores - http://www.anandtech.com/show/3863/amd-discloses-bobcat-bulldozer-architectures-at-hot-chips-2010/5
It did? Here I thought that for anything that doesn't make use of the new FMAD, FP performance was effectively halved per 'core' since it's the exact same FP resources as a Phenom II now shared between two integer cores - http://www.anandtech.com/show/3863/amd-discloses-bobcat-bulldozer-architectures-at-hot-chips-2010/5
Another thing to keep in mind the FPU in BD module is WAY more flexible then previous generation. It can do different types of float math no matter which half of the pipe it goes down. FMUL and FADD can be handled by both pipes. Whereas on stars core, I believe one pipe did FMUL the other FADD and the other FMISC.
So, BD is more flexible ..
At least thats how I see it based on my very limited uarch knowledge =P and just going off uarch diagrams =)
F@H I doubt uses anything but normal SSE or FPU math. It doesnt use AVX or FMA AFAIK...If it did then F@H would be significantly faster on a SB, which I dont think it is...