Bulldozers Weak/Strong points?

[Phynaz]

No, it was pointed by anand , and i checked
the slide on intel s site, and that was real...

Sure that it s somewhat annoying in respect
of your motto about Randy Allen....

Oh, you cherry picked one benchmark out of an entire article.

Okay then.

Sure that it s somewhat annoying in respect
of your motto about Randy Allen....

My "motto" as you call it, is a word for word quote. Why does it bother you so much?

 

[jimbo75]

Oh, you cherry picked one benchmark out of an entire article.

Okay then.



My "motto" as you call it, is a word for word quote. Why does it bother you so much?

One might ask why you feel the need to quote years old comments. Of course we already know why that is.

 

[Abwx]

Oh, you cherry picked one benchmark out of an entire article.

The point was about Fluent, since you denied barcelona
being better than a much higher freq. xeon in this applic.(50%!!)
At the end, there s a second bench , ls dyna that say
the same...:awe:

But perhaps sysmark or fritzchess are more relevant
than scientific applications making full use of the
cpu s capability..?....:biggrin:

 

[Phynaz]

One might ask why you feel the need to quote years old comments. Of course we already know why that is.

Good, then there's no reason to comment on it.

 

[JFAMD]

Possibly a big drawback of BD will be the turboboost. They will turboboost against TDP. So if the running applications are using less resources BD will clock higher and perform better.... but this means that BD will be relativly closer against its TDP compared to its competitor or predecesors. So it will be using alot more power on average with the same TDP as other cpu's. (intel on the other hand has a similar problem where the cpu's can go over TDP for a short periods)

I disagree. With the ability to boost all cores by up to 500MHz under load I find that to be a big benefit. With intel's implementation you really need to get down to 1 core to get close to that. With all cores actvie the boost is nominal at best.

 

[zebrax2]

Possibly a big drawback of BD will be the turboboost. They will turboboost against TDP. So if the running applications are using less resources BD will clock higher and perform better.... but this means that BD will be relativly closer against its TDP compared to its competitor or predecesors. So it will be using alot more power on average with the same TDP as other cpu's. (intel on the other hand has a similar problem where the cpu's can go over TDP for a short periods)

Yes it would use more power when doing the work but it will also finish the work faster thus power consumption with turboboost on and off for say a day would probably be the same or close enough

 

[drizek]

I disagree. With the ability to boost all cores by up to 500MHz under load I find that to be a big benefit. With intel's implementation you really need to get down to 1 core to get close to that. With all cores actvie the boost is nominal at best.

Yes, but

1. 500MHz means nothing if we don't know base clocks
2. People like us can run Intel CPUs overclocked at well past the max 1-core turbo frequency. Will the same be true for AMD?

 

[Joseph F]

I disagree. With the ability to boost all cores by up to 500MHz under load I find that to be a big benefit. With intel's implementation you really need to get down to 1 core to get close to that. With all cores actvie the boost is nominal at best.

So... what makes this any different than Cn'Q or SpeedStep?
If say the "Max" frequency on an AMD CPU is 3.0GHz and you get a 500MHz boost when all of the cores are active then how is this any different than the existing throttling technologies? Why not just market said CPU as 3.5GHz? Is there a limited amount of time to which the boost can occur?

 

[LiuKangBakinPie]

How not? It'll have 4 (2x2) FPUs and 4 integer cores. Two modules, for all intensive purposes, is a quad core.

2 modules inside the same package don't make it two. But great for marketing though

 

[AtenRa]

Microarchitecture-wise, bulldozer is a huge change, totally new core from the ground up. It won't just be a small improvement.

That said...the big unknown here is GloFo's 32nm process tech. That determines clockspeeds, yields, and power-consumption. So we have no way of knowing whether GloFo is going to do good by AMD or if they are going to be the achilles heel in the equation.

Unfortunately we do know GloFo went gate-first integration for HKMG which is known (as in "science" known, process technology and all that) to enable denser chips (same design by smaller die size) but at the expense of having lower drive currents (less clockspeed potential) compared to a gate-last integration.

So, while we don't know the specific parametrics of GloFo's 32nm HKMG SOI we do know enough to know that we should not be expecting to be surprised to the upside when it comes to clockspeeds and power-consumption comparisons to Intel's 32nm HKMG.

Nevertheless I remain steadfastly optimistic that the boys and girls in green have really pulled another K7 Athlon out of the hat here and we are going to see some 3.6GHz stock clock 8-core parts (turbo'ing up to 4.2GHz). Crossing my fingers on this one, really want to see it happen.

Perhaps thats the reason they have a wider microarchitecture pipeline design to compensate for the lower driver currents ??

So they will have a Gate-First (higher silicon density, more chips in the wafer) with HKMG (less leakage) and SOI (less leakage) 32nm process but lower drive current (lower Frequency).

Gate First will give them lower manufacturing cost but lower drive current (Less CPU frequency).
HKMG will give them less leakage (higher Frequency and better power consumption)
SOI will give them less leakage (higher Frequency and better power consumption)
Wider pipeline design will give them higher frequency to compensate from the Gate-First lower drive current in manufacturing.

what do you think ?

 

[Idontcare]

Perhaps thats the reason they have a wider microarchitecture pipeline design to compensate for the lower driver currents ??

So they will have a Gate-First (higher silicon density, more chips in the wafer) with HKMG (less leakage) and SOI (less leakage) 32nm process but lower drive current (lower Frequency).

Gate First will give them lower manufacturing cost but lower drive current (Less CPU frequency).
HKMG will give them less leakage (higher Frequency and better power consumption)
SOI will give them less leakage (higher Frequency and better power consumption)
Wider pipeline design will give them higher frequency to compensate from the Gate-First lower drive current in manufacturing.

what do you think ?

Yeah, to be sure there are a lot of high-level trade-offs going on here, and the best we can do is craft hypothetical if/then logic trees to bound the discussion. It can be enjoyable and profitable nevertheless, provided no one gets pedantic and takes us to task over the volumes of unstated caveats that stand behind each of our posts.

The crucial difference I see here is the SOI. SOI reduces the leakage, leaving more of their "TDP budget" available for cranking up the voltage (Idrive is Vcc dependent) so they hit higher clocks regardless the normalized disadvantage in Idrive that comes with gate-first.

Likewise, just as Idrive is a voltage-normalized metric it is also a transistor width normalized metric, so while gate-first reduces Idrive per micron width of the xtor it also gives you higher density xtor layouts meaning you have the option of maker your xtors "wider", making the die-size larger, and boosting your net drive current in the process.

You see this all the time in sram layouts and cell-size. Your L1$ sram cell size will be huge compared to the cell size (density) L3$ where clockspeed and latency are reduced.

Just look at AMD's 45nm non-HKMG enabled processors, they are bigger chips, and less dense, have higher operating voltages, and yet they fit inside the desired TDP envelopes and clock extremely well compared to Intel's 45nm chips.

This is why I say it is merely a concern, not an outright expectation of disaster, that GloFo went gate-first. Had they gone gate-last for 32nm, as they are expected to do for 22nm, then we know their Idrives would have been all the hotter and the possibility for higher clocks would have been all the higher.

But I suspect that thanks to SOI and the flexibility of making layout density tradeoffs they will have no problems getting their clockspeeds where they want them to be. It just might not happen with the first release of 32nm chips, it took them a year to get 45nm tweaked well enough to enable release of those 1075T's and 1090T's after all.

 

[JFAMD]

So... what makes this any different than Cn'Q or SpeedStep?
If say the "Max" frequency on an AMD CPU is 3.0GHz and you get a 500MHz boost when all of the cores are active then how is this any different than the existing throttling technologies? Why not just market said CPU as 3.5GHz? Is there a limited amount of time to which the boost can occur?

You should read my blog on turbo core.

The net issue is that when you bin a processor you have to take worst case scenario. If at max power it reaches 3GHz for a database, 2.8GHz for java and 2.4GHz for HPC you have to fuse it as a 2.4GHz, even though it could get more.

You can't market it as a 3GHz part and say "some workloads might be lower", there would be anarchy and violence in the streets if that started happening (i.e. lawsuits).

Turbo core let's you capture the power headroom and turn it into clock speed.

 

[piesquared]

http://www.globalfoundries.com/eBooks/dac_hkmg/

I also remember reading over a year ago that GF matched intel at 32nm. Obviously the yield situation wasn't so good.

There's a video series on those slides at GloFo.

http://www.globalfoundries.com/media/hkmg_videos.aspx

 

[Soleron]

^ Pretty sure that was me on a nice day back then too. Mr friendly, that's what they use to call me then

Can I just say it was me you were getting angry at, and I fully deserved it and was being an idiot then?

I figured it out when AMD actually released Phenom, because before that I hadn't seen tech companies lying OR prerelease benches being wrong. That was my first release cycle.

So I agree, no one should ever link back that far again.

 

[alyarb]

^ ZOMG we sure were a forum full of a bunch of hateful trollish asshats back then! D: (myself included ) Yikes! Not pretty, please don't link to threads that go back that far in the past ever again, there should be a statute of limitations on forum thread links. :|

hilarious

 

[drizek]

Guys no matter how you look at it, there can only be 2 outcomes:

outcome #1
the reason AMD is not leaking performance numbers is because barcelona is crap, and in that case AMD will lose so much market share to intel, that it just might be the end for them.

outcome #2
the reason AMD is not leaking performance numbers is because barcelona is so damn good that AMD wants to catch Intel completely unprepared. In that case AMD will gain so much market share to intel, that it will be back to K8 vs P4 days.



obviously I am hoping for the latter. I think everyone is for sake of out wallets.

...

 

[AtenRa]

Yeah, to be sure there are a lot of high-level trade-offs going on here, and the best we can do is craft hypothetical if/then logic trees to bound the discussion. It can be enjoyable and profitable nevertheless, provided no one gets pedantic and takes us to task over the volumes of unstated caveats that stand behind each of our posts.

The crucial difference I see here is the SOI. SOI reduces the leakage, leaving more of their "TDP budget" available for cranking up the voltage (Idrive is Vcc dependent) so they hit higher clocks regardless the normalized disadvantage in Idrive that comes with gate-first.

Likewise, just as Idrive is a voltage-normalized metric it is also a transistor width normalized metric, so while gate-first reduces Idrive per micron width of the xtor it also gives you higher density xtor layouts meaning you have the option of maker your xtors "wider", making the die-size larger, and boosting your net drive current in the process.

You see this all the time in sram layouts and cell-size. Your L1$ sram cell size will be huge compared to the cell size (density) L3$ where clockspeed and latency are reduced.

Just look at AMD's 45nm non-HKMG enabled processors, they are bigger chips, and less dense, have higher operating voltages, and yet they fit inside the desired TDP envelopes and clock extremely well compared to Intel's 45nm chips.

This is why I say it is merely a concern, not an outright expectation of disaster, that GloFo went gate-first. Had they gone gate-last for 32nm, as they are expected to do for 22nm, then we know their Idrives would have been all the hotter and the possibility for higher clocks would have been all the higher.

But I suspect that thanks to SOI and the flexibility of making layout density tradeoffs they will have no problems getting their clockspeeds where they want them to be. It just might not happen with the first release of 32nm chips, it took them a year to get 45nm tweaked well enough to enable release of those 1075T's and 1090T's after all.

Yeap,

Clearly from paper specs the GloFo 32nm process has an advantage over Intels 32nm HKMG. Since both have HKMG the SOI that GloFo uses compensate (due to less leakage) for the lack of Idrive current of the Gate-First process.
So at the end, GloFos 32nm could have the same Idrive current and denser transistor count than Intels 32nm.

The only advantage Intel has is their 32nm process incorporates the second HKMG generation (Gen one on 45nm) when GloFo is in the first attempt and they sure have more data and experience than GloFo in that field.

For the remain of the year, GloFos 32nm will be competitive with Intels 32nm and if Yields are good they could have the advantage but not the volume (Only one fab) to flood the market and gain a lot of market share.

They can be competitive until the end of H1 2012 even if Intel will start the 22nm at the end of 2011 due to a new low yield process. After that point they will not be able to compete against Intels 22nm process and they will have to wait for their own 22nm process and restart the same cycle.

 

[Dresdenboy]

Too early to call without real benches. If a somewhat in-depth preview/review doesn't appear before the end of April, either the release date is in jeopardy or the performance is well below expectations. Already I am a little nervous with the lack of benches.

Could you please provide some empirical analysis over the last decades of a relation between launches, expectations, preliminary information and achieved performance after launch?

I just looked at AT and Anand did a pretty nice preview of the Nehalem tech 5 months before it launched! BD is no where to be seen and it is LESS than this far away. Silence is usually worrisome.

I wonder if Intel could do that if there would be no competitor (Osbourne effect). Otherwise they could justify price cuts in advance to an upcoming launch.

 

[Idontcare]

I just looked at AT and Anand did a pretty nice preview of the Nehalem tech 5 months before it launched! BD is no where to be seen and it is LESS than this far away. Silence is usually worrisome.

I wonder if Intel could do that if there would be no competitor (Osbourne effect). Otherwise they could justify price cuts in advance to an upcoming launch.

I had assumed the nehalem "leaks" were orchestrated to undermine potential sales of PhenomII at the time.

Intel only does things to make money, I think we can all agree on this, so its not a matter of questioning whether or not the early-leak efforts on their part are done to increase revenues somehow or at sometime.

Rather the only real mystery left for us to contemplate is the question of just how devilishly profitable such tactics pay off for Intel, at their competitors expense.

The fact that AMD can keep leaks under wrap is proof that Intel could do the same, maybe even more so since they've got more thumb to apply on the matter (it is this way in the process development arena, Intel applies ample thumb to their vendors to keep in-house secrets from spreading).

 

[grimpr]

I think AigoMorla has lots of stories to tell about Intels Securitate.

 

[exar333]

I had assumed the nehalem "leaks" were orchestrated to undermine potential sales of PhenomII at the time.

Intel only does things to make money, I think we can all agree on this, so its not a matter of questioning whether or not the early-leak efforts on their part are done to increase revenues somehow or at sometime.

Rather the only real mystery left for us to contemplate is the question of just how devilishly profitable such tactics pay off for Intel, at their competitors expense.

The fact that AMD can keep leaks under wrap is proof that Intel could do the same, maybe even more so since they've got more thumb to apply on the matter (it is this way in the process development arena, Intel applies ample thumb to their vendors to keep in-house secrets from spreading).

I understand AMD has been bitten by over-hyping previous CPUs, but so has Intel. Phenom I and Prescott were great examples of these from both groups, but not giving any preview data out reeks of insecurity of their competitiveness. This is my opinion, not fact. If BD is a great product, why not make more people think twice about getting a SB system now? AMD has been somewhat secretive in the past, and that is understandable, but I wonder if they lose out somewhat by not giving more information out.

BD has to be the biggest launch for AMD since the A64 was initially released. Again, looking back on AT history Anand did a review in September for the December A64 CPUs. Although I am interested in BD, I could care less about waiting on any builds for it to be released without some numbers. I know a couple different people that need computers ASAP and there is no compelling reason to wait for BD based on current data available, period. AMD is losing out if you ask me. To reiterate, this is my opinion. AMD has their own business strategy, but as an enthusiast, it is pretty crappy for us waiting for the latest and greatest.

 

[exar333]

Could you please provide some empirical analysis over the last decades of a relation between launches, expectations, preliminary information and achieved performance after launch?


I wonder if Intel could do that if there would be no competitor (Osbourne effect). Otherwise they could justify price cuts in advance to an upcoming launch.

No thanks, and this doesn't really address what I said. Past actions do not dictate future performance. AMD was similarly forthcoming with A64 and Phenom and we all know how differently those launches went.

 

[Topweasel]

I understand AMD has been bitten by over-hyping previous CPUs, but so has Intel. Phenom I and Prescott were great examples of these from both groups, but not giving any preview data out reeks of insecurity of their competitiveness. This is my opinion, not fact. If BD is a great product, why not make more people think twice about getting a SB system now? AMD has been somewhat secretive in the past, and that is understandable, but I wonder if they lose out somewhat by not giving more information out.

BD has to be the biggest launch for AMD since the A64 was initially released. Again, looking back on AT history Anand did a review in September for the December A64 CPUs. Although I am interested in BD, I could care less about waiting on any builds for it to be released without some numbers. I know a couple different people that need computers ASAP and there is no compelling reason to wait for BD based on current data available, period. AMD is losing out if you ask me. To reiterate, this is my opinion. AMD has their own business strategy, but as an enthusiast, it is pretty crappy for us waiting for the latest and greatest.

Easy Intel didn't care if it stopped people from buying their product for a couple months, just as long as it stopped people from buying AMD. They did it before, if Anyone remembers the K7M, they would remember that for about 4 months it came in a White box. Intel had made it known that they were "experiencing chip-set shortages" and that any Mobo manufacturer partnering with AMD might see reduced allotment. Same with OEM's and their vouchers and upper-end hardware. Intel is always selling enough hardware, but any loss in sales for AMD is big and keeps AMD from being able to compete with them. Lost CPU sales there pays dividends down the road.

Its literally why AMD has said that it isn't about what Intel is doing now or competition now (back when AMD was winning) its about what they did 10 years ago that has helped stifle their ability to maximize their at the time superior product. I remember when the K6-2 was popular the CEO said at the time when asked if Compaq said that wanted to use all AMD CPU's what he would do, his answer was decline it. Its not like AMD could just flip a switch and turn up production (something I heard a lot with the Wii shortages). Years of being pushed into the red or barely in the black, means that AMD has to move very very slowly. Hopefully that changes as GloFlo competes more with TSMC and AMD can move around a bit to other foundries and get more CPU's and jump earlier on new processes.

For AMD though announcing and Benchmarking a new CPU before its ready to launch if its faster stalls CPU sales, the AMD ones would hurt them and the Intel ones would have almost 0 impact on Intel. If its slower, it just sends people to i5's and i7's that much faster.

 

[formulav8]

Intel gave a major heads-up when it came to core2 performance. They even gave anand and other reviews sites a free x6800 extreme cpu. That was months before Intel finally released core2.

Anyways, I keep having a nagging feeling bd will be delayed one way or another. I just have a feeling that llano will be released before bd even though bd is scheduled to release first. It would still be nice to get some numbers on bd. Even a 1MB SuperPI bench would be something.

Hopefully things will go Perfectly for AMD this go round. :thumbsup:

 

[IntelUser2000]

I just have a feeling that llano will be released before bd even though bd is scheduled to release first. It would still be nice to get some numbers on bd. Even a 1MB SuperPI bench would be something.

Actually Llano is shipping in volume already.