Bulldozers Weak/Strong points?

[formulav8]

Based on known data, slides, ect., what will be Bulldozers Weak Points and Strong Points, I guess compared to PII/SB? Plus what tasks will Bulldozer seem to do good/bad in? I know we won't know for sure until release, but many people can predict based on specs and such. Thanks

 

[Vette73]

Still not enough info IMO.

I still think it will offer more cores for the dollar and beat intel dollar to dollar on things that can use a lot of cores. But lowwer single thread items will probable be better on intel.

 

[LxMxFxD4]

Still not enough info IMO.

I still think it will offer more cores for the dollar and beat intel dollar to dollar on things that can use a lot of cores. But lowwer single thread items will probable be better on intel.

^this.

Like previous AMDs it will

1. Run hotter
2. have faster FPU
3. Be cheaper than Intel's current offering
4. Cause problems with about 5% of all existing windows software on launch day.
5. Crush in the server market.

 

[nenforcer]

^this.

Like previous AMDs it will

2 have faster FPU

This is now in debate because of what they have done in order to save die space (and power) is share the FP unit among all the cores. Shouldn't have a dramatic effect on Server CPU's and is probably ideal but I'm guessing they are banking on their previous strong performance in this area for the desktop CPU's (i.e. gaming performance).

 

[VirtualLarry]

4. Cause problems with about 5% of all existing windows software on launch day.

When has ANY AMD CPU had that problem? I certainly don't remember any.

 

[Elixer]

^this.

Like previous AMDs it will

1. Run hotter
2. have faster FPU
3. Be cheaper than Intel's current offering
4. Cause problems with about 5% of all existing windows software on launch day.
5. Crush in the server market.

I fixed your list for you.

 

[podspi]

There shouldn't be any bottlenecks with the flex-FPU in 128 bit code, it's only when two threads are running 256 bit code in the same module that potential bottlenecks occur.

Somebody correct me if I'm wrong, but if both threads start using 256 bit code (or one thread 256 bit and one thread 128 bit) some sort of SMT-occurs. We finally get (kinda) SMT in an AMD CPU :awe:


I do agree that Bulldozer's FPU will be (hopefully) the weakest link in the core, but this is consistent with AMD's vision of the future. The FPU isn't terribly important in most server applications, and AMD's next high-volume consumer chip with Bulldozer-based cores (Trinity) will have a relatively huge and powerful number-cruncher attached to it, making the FPU less important (pending software adoption, of course). Current HPC software should be much faster on BD (assuming they didn't break existing 128 bit) and future HPC should run happily on their Radeon line :biggrin:

 

[SickBeast]

Somebody correct me if I'm wrong, but if both threads start using 256 bit code (or one thread 256 bit and one thread 128 bit) some sort of SMT-occurs. We finally get (kinda) SMT in an AMD CPU :awe:

I think in reality what would happen is that the two data streams would have to "take turns" using the FPU, in a sense. It won't be like SMT in that there will not be a performance boost of any kind. If anything it will be detrimental.

 

[podspi]

I think in reality what would happen is that the two data streams would have to "take turns" using the FPU, in a sense. It won't be like SMT in that there will not be a performance boost of any kind. If anything it will be detrimental.

That's pretty much what SMT is. Compared to two independent cores, there isn't any performance boost, but compared to one core there IS an increase in throughput. Keep in mind that a Bulldozer module has about as much floating-point capability as a Sandy Bridge core (both in 256 bit mode).

The clever bit is that there really isn't any 256bit AVX code floating around in the real world, so instead of having an FPU capable of 256bit or 128bit (or less) code (like Sandy Bridge), AMD put two 128bit FPUs in a module and allows them to be ganged together for 256bit instructions.

So when we have two threads, each using the FPU in 128 bit mode, they can execute at the same time, but if one of them is executing 256-bit code, they need to resort to SMT -- which will decrease performance.

In other words, for integer ops a module looks like two cores, for FP 128 bit and less a module looks like two cores, but for FP 256 bit a module looks like one core.

Please someone correct me if I am misunderstanding how the Flex-FP works. :biggrin:

To clarify, SickBeast I'm not disagreeing with you (I think everything you said was correct), I'm just viewing the module as less than 2 full-blown cores capable of 256bit FP instructions, which is why they have to resort to something at least similiar to SMT for FP). I have a feeling that SMT for FP will be more effective than SMT for integer+FP, at least for FP instructions that wouldn't benefit too much from GPGPU.

 

[Tuna-Fish]

Somebody correct me if I'm wrong, but if both threads start using 256 bit code (or one thread 256 bit and one thread 128 bit) some sort of SMT-occurs. We finally get (kinda) SMT in an AMD CPU :awe:

Actually, the way I'm reading it, the FPU schedules the ops without caring which core they come from. So the FPU is always doing SMT. This is based especially on the chapter 2.11 on the "Optimization guide for fam 15h processors".

 

[Tuna-Fish]

The way I understand it, the FPU receives 4 ops per clock from one core. These might be statically partitioned, or at least statically partitioned unless one core has no ops to send, as this would guarantee a degree of fairness to the FPU. Once the ops hit the scheduler, the only way the ops from different core differ is that they refer to different registers. The scheduler then reorders the ops as it pleases and picks ones whose operands are ready to execute without regard to the core that originated the ops.

 

[Lobo56]

I think its too early to call.

Ideally though I would love to see it destroy Sandy Bridge as much as possible. Why? Because it would give Intel a reason to perhaps move forward their plans for 6+ core LGA2011 CPU's or even bring Ivy Bridge forward a few months to try reclaim the performance crown.

 

[LxMxFxD4]

When has ANY AMD CPU had that problem? I certainly don't remember any.

Are you joking?

How many AMD chipsets/cpus required countless driver updates to get working with windows. I seem to remember.. all of them. Yes AMD eventually gets stable but takes a while.

 

[Chiropteran]

Are you joking?

How many AMD chipsets/cpus required countless driver updates to get working with windows. I seem to remember.. all of them. Yes AMD eventually gets stable but takes a while.

In my experience, none of them. There was an issue with VIA chipsets and soundblaster cards way back that caused a lot of crashes, but VIA is not AMD.

Yes, there are minor issues with the SATA controller and such today, but they certainly don't require any driver updates or work to get windows running. Windows runs fine right out of the box, you can't even see any sort of problem unless you look really hard for it, afaik it's just a minor performance penalty when using certain drives in AHCI mode. I never would have known it from using my system, if not for reading about it on the forums.

 

[Cerb]

Are you joking?

How many AMD chipsets/cpus required countless driver updates to get working with windows. I seem to remember.. all of them. Yes AMD eventually gets stable but takes a while.

What ones? The only one I know of was the 740G bug (I don't even remember what it did, off-hand--something about 4GB of RAM and using IGP causing...something?), and I've used many AMD chipsets. It was when AMD chipsets weren't an option ($ initially, and performance later on) that I've had problems.

 

[Lonbjerg]

I remember a dual core AMD CPU patch:
http://www.xtremesystems.org/forums/showthread.php?t=81429

 

[ShadowVVL]

I never had any issues with amd or intel but then again I never bought them the day they hit the shelf.

I think I will skip both amd and intel cpus this year and go with IB once the mobos have been proof tested.unless BD somehow blows past SB but i doubt it.

 

[out.of.order]

Based on known data, slides, ect., what will be Bulldozers Weak Points and Strong Points, I guess compared to PII/SB? Plus what tasks will Bulldozer seem to do good/bad in? I know we won't know for sure until release, but many people can predict based on specs and such. Thanks

weak point: isn't yet released

strong point: cause isn't yet released, we can suppose superlative performance :biggrin:

 

[Edrick]

weak point: isn't yet released

strong point: cause isn't yet released, we can suppose superlative performance :biggrin:

This.

Still vaporware until late June (so I heard).

But FMA is a stong point in my opinion.

 

[Anarchist420]

A major weak point is the slow L3 cache. There is a lot of it, but it's slow. I wouldn't be surprised if Bulldozer is only 20% faster per clock than the PII architecture.

 

[IntelUser2000]

A major weak point is the slow L3 cache. There is a lot of it, but it's slow. I wouldn't be surprised if Bulldozer is only 20% faster per clock than the PII architecture.

/core?
/GHz?
/Anarchist420 points?

 

[ShadowVVL]

Didn't they say the L2 was faster and would make up for it?

 

[dguy6789]

Are you joking?

How many AMD chipsets/cpus required countless driver updates to get working with windows. I seem to remember.. all of them. Yes AMD eventually gets stable but takes a while.

Have you really been here since 2007? Your posts sound like you're extremely new to computers. These problems you're talking about have never happened.

 

[formulav8]

Is anything known whether AMD truly beefed up its integer performance? IIRC that has been a major advantage Intel has had since Conroe.

 

[Topweasel]

A major weak point is the slow L3 cache. There is a lot of it, but it's slow. I wouldn't be surprised if Bulldozer is only 20% faster per clock than the PII architecture.

If they can pull that off and clock it as high as I think they intend to be able to clock it, that would be a fantastic result.