Originally posted by: ribbon13
No Zepper... I meant a PATA->SATA Adapter. Notice the graphs->
http://www.techimo.com/articles/index.pl?photo=44
Actually, those graphs and the explaination given, is most likely incorrect.
The statement about PATA lacking error-correction is blatantly false, that's one of the principle things that was added to the UDMA specs, was a CRC check on the data-transfer, both the drive and the host controller calculate it, and if it mis-compares when they are done, then a UDMA CRC error has occured, and the transfer is re-sent. I'm not familiar with that benchmark in specific, so I'm not sure what the time-scale reference is, compared to HDTach 2.61 (which I am familiar with), but those smaller downward spikes on the PATA graph, look like nothing more than standard IDE activity overhead on a shared PATA IDE channel to me. The only way to find out for sure, is to check the drive's SMART status, and look at the raw count for the UDMA IDE CRC error attribute, and check it both before and after the tests (and check the Windows' System Event Log too). Since we don't have that data, one cannot make that statement conclusively, but it should be clear enough that the explaination given as stated is blatantly incorrect. In fact, one of the fellows on the T13 ATA committee, has on his home page some interesting data that suggests that data-transmissions over the SATA cables used today, are actually
less error-free than proper PATA cabling.
So IMHO, that's all marketing BS. But I'm not knocking the utility of moving your drives onto a SATA channel. Only that the "improved" graphs shown, are only because the SATA channels don't share with anything else, unlike PATA, and likely has nothing to do with cable signal-integrity or errors.
Edit: to add that in a normally-functioning PATA system, you shouldn't be getting any UDMA CRC errors in the first place anyways, which is another reason why the explaination given is marketing BS, because it implies that those errors are somehow commonplace. (If those spikes in the graph are actually from CRC errors, which I highly doubt. If they were, I would think that they would go all the way to the bottom of the graph.)
Edit 2: Just wanted to add that I'm not in any way against using an IDE-to-SATA converter, I think that's a great idea. Just that the marketing explaination given for it, doesn't really wash.