Originally posted by: Idontcare
Originally posted by: MODEL3
Sorry, I tried to open the file and it doesn't open with any programs that i have!
I googled ppt and it seems that i need to have powerpoint (I don't even have word) :laugh:
Sorry, yeah it is a powerpoint file but just like with adobe acrobat files in which you can download acrobat reader for free to open the pdf file you can download
Microsoft Powerpoint Viewer for free to open and view any powerpoint files.
Originally posted by: MODEL3
Since, you said that the ICs are either 8bit (1 byte) or 16 bit (1 word),
doesn't that mean that 2 ICs are either 16bit or 32bit?
As TSCenter mentioned, which feeds into my comment above regarding memory organization, the memory on the card you are referencing is x32 (specifically 8Mx32) which means each IC is 32bit I/O. Two such chips would give you the 64-bits of I/O you'd need to interface with a 64bit memory controller.
If you go to
http://www.dramexchange.com/ you'll see by far the more common memory organization for commodity dram and nand flash is the x8 organization. The fact that the 4350 doesn't use commodity grade x8 chips already confirms for you that your earlier point regarding the need to use commodity chips is in fact not always the case as you have proof they use x32 organization on that AMD board.
To get 48bit they could be using three x16 chips, or six x8 chips. What they use will depend on the total dram capacity they want to install combined with the dram density of the chips they order from the manufacturer among other cost-driven decisions such as pincount and PCB layout (real-estate). Likewise to get 96bit I/O they could easily go with three x32 chips, six x16 chips or twelve x8 chips.
I tried to open it with acrobat (i had it already in my pc) but it can't read it! (maybe i have an older version?) Anyway it doesn't matter!
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Well at first, you confused me saying that the there are
only two possibilities[/u]!
Originally posted by: Idontcare
I could be wrong here but isn't the bus bit for an individual IC either 8bit (1 byte) or 16 bit (1 word)?
For example desktop Dimms are 64bit buses but the actual bit bus of the individual IC's on the dimms depends on the organization (x4, x8, or x16 are common organizations).
Now, you added the possibility to be 32bit!
Well if we add this possibility your scenario makes sense!
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Can you explain to me another thing?
In the link you provided the 1GB is consisted from 16 or 32 pieces of ICs (non ECC) ,
in that case, in order the sum to be 64bit, each IC must have 2bit or 4bit bandwidth!
So we have to add in the possibilities, the 2bit and the 4bit!
So in order to be your logic correct (
that each IC can communicate with memory bandwidth that is lower than 64bit) we have to reject your original scenario that:
bus bit for an individual IC either 8bit (1 byte) or 16 bit (1 word)
and add in your original scenario 3 more possibilities:
2bit
4bit
32bit
Are you absolutely sure that each IC can
communicate with bandwidth that is lower than 64bit?
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You said:
Originally posted by: Idontcare
the memory on the card you are referencing is x32 (specifically 8Mx32) which means each IC is 32bit I/O
According to my understanding, it doesn't mean that! (i may be wrong, afterall you are the engineer!)
As i already told you the ICs are
only 2 in the 4350!
The above term
8Mx32 has
nothing to do with the memory bandwidth that the DDRAM is
communicating with the memory controller!
It just means that
each IC (
256MBytes) has the following:
1. Each memory chip is essentially a matrix of tiny cells!
2. Each tiny cell holds one bit of information! (in the worst case scenario)
3. And since memory chips are described by how much information they can hold, we call this "
chip density"!
4. The expression
"8Mx32" it just describes what type of density we have!
It describes one kind of 256Mbyte chip (in this case) in more detail!
it just describe how the memory cells are divited!
5. 8M means 8 million cells,
and X 32 means that
each cell being 32bit in width!
6. The fact that the cell is 32bit in width,
it doesn't mean that the DDR technology must communicate at 32bit! (That's why it needs 2 ICs in order to achieve the 64bit number!
On the contrary, the DDR tech (STANDARD TYPE) can communicate "
efficiently" only at 64bit or multiples of 64bit!
I mean that the width of the cell
doesn't necessarely mean that the communication bandwidth automatically is the same!
It can be anything multiply of the cell width!
In the case of
DDR tech the
communication number standard is 64bit at the time! (the data being transferred 64 bits at a time
always)
That's why we never saw before 48bit types of memory bandwidth in GPUs!
At least that is my "point of view"!
But like i said before, since i don't have a technology backround and since you are an Engineer, probably i am wrong!
In this case again,
the possibilities the 48bit scenario to happen is next to zero!
Because, like you said the 48bit scenario will need
3 or 6 chips!
The 64bit needs just 1 or 2 chips, this 48bit scenario will add the cost certainly,
which is not a good thing since we are talking for below 50$ GPUs!
Also since the 4350 is already bandwidth limited at 64bit, I can imagine that the 4350 will be even more bandwidth limited at 48bit,
so what this mean for a future much faster DX11 architecture?
It means that the "5350" will be extremely bandwidth limited!
Imagine the scenario (worst case) that the "5350" will have 8 ROPs instead of the 4 ROPs of 4350!
Anyway, we will see at the launch date.