Originally posted by: Idontcare
Originally posted by: MODEL3
Well at first, you confused me saying that the there are
only two possibilities[/u]!
Originally posted by: Idontcare
I could be wrong here but isn't the bus bit for an individual IC either 8bit (1 byte) or 16 bit (1 word)?
For example desktop Dimms are 64bit buses but the actual bit bus of the individual IC's on the dimms depends on the organization (x4, x8, or x16 are common organizations).
Now, you added the possibility to be 32bit!
Well if we add this possibility your scenario makes sense!
Ah, I think I see the source of confusion. I was discussing x8 and x16 memory organization as a means to explain to you why it is that YOU most commonly see 64bit interfaces with conventional commodity dram IC's.
At the same time, armed with this new understanding of how memory is organized and ranked, I was thinking it would be a straightforward leap then to understand why and how it is that other organizations of dram exist and the purpose they serve.
Its an inclusive versus exclusive thing. You are trying to equate 64bit dram standards as being exclusive the existence of any other configuration, which is not the case. 64bit is but one possible configuration, and can be arrived at with any 2^n organization structure of the IC's used.
The actual organization (that is the number that
proceeds the "x" in the memory configuration, i.e. x32 vs x16 vs x8) of the IC's is usually intentionally selected such that the IO bit bus is matched (four x16 chips for 64bit, or eight x8 chips for 64bit, etc) to the desired capacity (that is the number that precedes the "x" in the memory configuration, i.e.
8Mx32 or
128Mx8) multiplied by the total number of IC's involved and then divided by the rank.
A dual-ranked memory configuration for example basically throws away half the potential IO bit bus but has the capacity. For example a dual-rank dimm will have 16 chips on it, but all those chips will be x8 organization. So the potential IO bus is 128bit, but because it is dual-ranked only half of the chips are addressable at a time, thus the IO is 128/2 = 64 bit in this case. But the user still gets to take advantage of the extra IC's in that the overall dimm capacity is 2x what it would have been had the dimm been designed as single-rank with only eight x8 chips.
That is all I was trying to communicate with that link to the presentation by asking you to just focus on those two slides, to better understand the meaning and utility of the terms rank and organization when it comes to memory ICs.
Originally posted by: MODEL3
The above term 8Mx32 has nothing to do with the memory bandwidth that the DDRAM is communicating with the memory controller!
It just means that each IC (256MBytes) has the following:
1. Each memory chip is essentially a matrix of tiny cells!
2. Each tiny cell holds one bit of information! (in the worst case scenario)
3. And since memory chips are described by how much information they can hold, we call this "chip density"!
4. The expression "8Mx32" it just describes what type of density we have!
It describes one kind of 256Mbyte chip (in this case) in more detail!
it just describe how the memory cells are divited!
5. 8M means 8 million cells,
and X 32 means that each cell being 32bit in width!
6. The fact that the cell is 32bit in width, it doesn't mean that the DDR technology must communicate at 32bit! (That's why it needs 2 ICs in order to achieve the 64bit number!
On the contrary, the DDR tech (STANDARD TYPE) can communicate "efficiently" only at 64bit or multiples of 64bit!
I mean that the width of the cell doesn't necessarely mean that the communication bandwidth automatically is the same!
It can be anything multiply of the cell width!
In the case of DDR tech the communication number standard is 64bit at the time! (the data being transferred 64 bits at a time always)
That's why we never saw before 48bit types of memory bandwidth in GPUs!
An x32 organized chip can be used in a 32bit bus as a standalone chip. It just means it isn't configured to operate as a 64bit standard DDR interface. There really isn't anything magical about this. I could design my memory controller to interface a single x32 IC or two x32 IC's or three x32 IC's (resulting in a 32bit, 64bit, or 96bit bus).
If I wanted to describe my device as being DDR 64bit IO compliant then I better do it as two x32 IC's so I'm not lying, but thats the point, once I build it all I need to is spec it out properly and everyone in the industry would inherently understand what I did. If I spec it out as a 96bit IO device then no one is going to raise an eyebrow.
Now DDR dimms for your desktop computer are speced out as being 64bit. So if everyone is going to use x8 organized IC's then your dimm had better have eight IC's on it. But you could have just as easily used x16 organized IC's on your dimm, albeit you'd only stick four IC's on the dimm (if you wanted to keep it as rank 1, otherwise you'd put eight x16 IC's on the dimm and it would become a rank 2 dimm to maintain 64bit IO compliance). Alternatively you could build your dimm with x32 organized IC's, albeit you'd just use two such IC's.
The difference here is capacity, if the density of x32 organized IC's is a scant 128M then your dimm is going to be a paltry 256M dimm, probably not a big market for dimms with only 256M on it. But if the density of x8 organized ICs is the same paltry 128M but you get to pack eight of them onto a dimm then you get the same 64bit IO but 4x more capacity (a 1GB dimm in this case).
This is true with GPU's as well, the organization of the GDDR IC's is intentionally selected (contracted) so that the capacity and the IO bus width match. At that point it just becomes a matter of cost. Choose to large of an IO bus and you have to pack (buy) so many IC's of the correct organization to match the aggregate IO and now your GPU needlessly costs a ton. Choose too low of an IO bus and you might not be able to get the density you want at the organization footprint you have to match your IO bus, resulting in a meager ram capacity board or you go dual-rank (or higher) and buy the capacity but throw away the potential IO bandwidth.