- Feb 13, 2011
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Let's look at Skylake-DT and Z170, for example. The CPU has 16 dedicated PCIE lanes integrated into it and the Z170 chipset has an additional 24. That's a total of 40 lanes.
So, what's stopping x8/x8/x8/x8 PCIE? why can't the lanes on the chipset be utilized?
Now, even though I don't properly understand why, I also know there are weird chipsets that "add" PCIE lanes and enable weird things lime four-way SLI on mainstream CPUs. How does this work, exactly?
So, what's stopping x8/x8/x8/x8 PCIE? why can't the lanes on the chipset be utilized?
Now, even though I don't properly understand why, I also know there are weird chipsets that "add" PCIE lanes and enable weird things lime four-way SLI on mainstream CPUs. How does this work, exactly?