Idontcare, a technical explanation please?

[Arachnotronic]

Exophase,

112.5nm for Intel's 32nm M1 (this was the same as contacted gate pitch).

 

[Khato]

Glofo and TSMC at 14nm will keep the same Metal Pitch of the 20nm (64nm) and will only use a smaller Gate Pitch. That will still give them higher density than 20nm process but not in the order of 2x like they will have from 28nm to 20nm.

Some rather broad metrics for both TSMC's 20nm SoC and 16nm FF in comparison to their 28nm HPM are available on page 19 of this presentation. (You have to derive the 28nm to 20nm figures as both comparisons are to the 16nm process.) They're basically claiming 1.8x scaling down to 20nm (SRAM size meanwhile only scales ~1.57x from .127um^2 to .081um^2) and either a 15% increase in speed at same power or a 14% decrease in power at same speed. Other interesting point there is that the 16nm vs 28nm comparison numbers are quite similar to those Intel provided for their 22nm vs 32nm comparison.

Oh, and here is one of the sources for Intel17's statement that Intel will see the expected density scaling with 14nm. In fact, it states that Intel projects roughly the same scaling factor for the 10nm node as well. (Page 13 for density scaling, then pages 10 and 17 have some interesting tidbits too.) Credit to Intel17 for catching this nice little investor presentation.

 

[Exophase]

Exophase,

112.5nm for Intel's 32nm M1 (this was the same as contacted gate pitch).

Okay, so close to exactly the doubling point (very close to sqrt(2)). 80->64 is not nearly as close though, doubling would be more like 56-57nm. It's maybe close enough to where Intel could say it's about as good and it'd be an accurate statement, but still not quite.

I might coming off as blowing this out of proportion this but wouldn't you expect it to result at least slightly worse scaling in cases that are M1 limited? To get the same scaling on average it'd either need to have no cases that are M1 limited or the scaling in other cases would have to be even better to counteract it.

 

[Arachnotronic]

Okay, so close to exactly the doubling point (very close to sqrt(2)). 80->64 is not nearly as close though, doubling would be more like 56-57nm. It's maybe close enough to where Intel could say it's about as good and it'd be an accurate statement, but still not quite.

I might coming off as blowing this out of proportion this but wouldn't you expect it to result at least slightly worse scaling in cases that are M1 limited? To get the same scaling on average it'd either need to have no cases that are M1 limited or the scaling in other cases would have to be even better to counteract it.

Exophase,

Intel hasn't actually released any information re: pitch size, but 64nm is the tightest they can do with double patterning. Intel could bite the bullet and do triple patterning to get ~48nm M1 pitch, but that's not typically their style - to increase costs significantly like that.

 

[VirtualLarry]

^--22-nm IntelThe TSMC 28-nm process uses the same HKMG setup as Intel 32-nm.

What do you all think? Since Intel is skipping 14nm for the desktop chips, and instead, targeting mobile, will they even bother to develop the high-power / high-freq process node at 14nm for desktop? Or will they save massive R&D by skipping it, and only going for low-power nodes for mobile chips at 14nm?

 

[Arachnotronic]

What do you all think? Since Intel is skipping 14nm for the desktop chips, and instead, targeting mobile, will they even bother to develop the high-power / high-freq process node at 14nm for desktop? Or will they save massive R&D by skipping it, and only going for low-power nodes for mobile chips at 14nm?

No, Intel is developing a high performance 14nm node. Skylake LGA, Broadwell-E, Knights Landing, etc. all will use this process. Even Broadwell mobile uses the high performance process, AFAIK.

 

[Idontcare]

A lot of good stuff in this thread :thumbsup: Don't see where I really need to weigh in at this point because I think pretty much all the corners have been amply covered by so many of our fellow forum colleagues. (regarding the OP's request for my specific input)

Engineering involves a lot of trade-offs. Cost-benefits analyses and so forth. Density won't be solely determined by metal and gate pitches, true they are critical factors but they are not the sole factors.

One needs to also understand there are no real hard limits in lithography. Even the 64nm (double) and 48nm (triple) numbers thrown around are not hard limits. They are numbers defined by confidence limits and so on with respect to a cost-basis for securing a given level of yield entitlement versus the added cycle time costs of reworks (reprinting wafers if the litho step doesn't produce an image that meets internal specs).

It is possible that Intel has lowered its required entitlement yield target, thus enabling the use of sub-64nm pitch double-printing. Or it is possible they are going with higher RI immersion litho, etc.

There are lots of things that go into making decisions on engineering. Everything is just a matter of money. Truly and literally.

 

[Arachnotronic]

A lot of good stuff in this thread :thumbsup: Don't see where I really need to weigh in at this point because I think pretty much all the corners have been amply covered by so many of our fellow forum colleagues. (regarding the OP's request for my specific input)

Engineering involves a lot of trade-offs. Cost-benefits analyses and so forth. Density won't be solely determined by metal and gate pitches, true they are critical factors but they are not the sole factors.

One needs to also understand there are no real hard limits in lithography. Even the 64nm (double) and 48nm (triple) numbers thrown around are not hard limits. They are numbers defined by confidence limits and so on with respect to a cost-basis for securing a given level of yield entitlement versus the added cycle time costs of reworks (reprinting wafers if the litho step doesn't produce an image that meets internal specs).

It is possible that Intel has lowered its required entitlement yield target, thus enabling the use of sub-64nm pitch double-printing. Or it is possible they are going with higher RI immersion litho, etc.

There are lots of things that go into making decisions on engineering. Everything is just a matter of money. Truly and literally.

Idontcare, the man himself!

What other factors affect density from your experience? What do you think Intel could be doing at the 22nm node to get away with an 80nm M1 pitch?

 

[Idontcare]

What other factors affect density from your experience? What do you think Intel could be doing at the 22nm node to get away with an 80nm M1 pitch?

The 80nm M1 pitch is a matter of trade-offs. Anyone can do it, they just have to accept the resulting hit to yield, depth-of-field for resist thicknesses and planarity (affected by everything from CMP to metal height versus etch taper to sidewall roughness), and cycle-time for reworks and so forth.

Numbers that get presented as hard-numbers (like they are insurmountable barriers or limits) are to always be considered suspect. The numbers are only meaningful within a specific set of operating caveats and assumptions (which are usually not communicated alongside the hard-numbers themselves) and one can quickly become convinced things are set in stone when in reality it is just one big huge spectrum of possibilities accompanied by an associated spectrum of engineering tradeoffs and costs.