I would expect it to be more Cloud; either selling directly to cloud companies exclusively or maybe their own service. Or both.
Seriously, 200 watts more than 5900x? That is absurd.Yes, spotted. Until a retail sample gets passed around like a candy tray and we see actual benches, I don't care enough to speculate. If it's faster than a 5900X but uses 150-200 watts more, then it's DOA to me. While you don't have to worry about power consumption on a desktop, there is a limit to how silly you can get with power draw. I'm not trying to outbattle my dang central air.
Your over selling intels decode, it has been 4+1+1+1 uop's with 16bytes from L1i where heaps of basic instructions cant be done by the simple units because they decode into 2 uops, compared to Zen which is 2+2+2+2 + mircocode engine with 32bytes from L1i. Now intel are going to ????? in terms of decode but there are 6 of them and making the uop cache much closer to Zen2/3. So given intel/golden can now deliver 8uops from the uop cache a cycle just like Zen im going to say there front ends are probably pretty similar in terms of uop throughput a cycle.I dare say that GoldenCove is the biggest update since Conroe (Core2). Conroe (2006) introduced a 4-way x86 decoder, so from Conroe (Core2) to SunnyCove (2021) the x86 decoder was 4-way. I would like to add that from the time of Bulldozer (x86 CMT core (called module)) to Zen-Zen3 the x86 decoder is also 4 way. For the first time in 15 years in x86 history, Intel extended the x86 decoder by 50% to 6-way. This is really a very big x86 core upgrade. Additionally, Intel for the first time since P6 (Pentium Pro) to SunnyCove is switching from L1-I cache fetching 16 Bytes per clock cycle to fetching 32 Bytes in GoldenCove. GoldenCove is the largest redevelopment and expansion since Conroe (Core2). SandyBridge wasn't that revolutionary.
I dare say that GoldenCove is the biggest update since Conroe (Core2). Conroe (2006) introduced a 4-way x86 decoder, so from Conroe (Core2) to SunnyCove (2021) the x86 decoder was 4-way. I would like to add that from the time of Bulldozer (x86 CMT core (called module)) to Zen-Zen3 the x86 decoder is also 4 way. For the first time in 15 years in x86 history, Intel extended the x86 decoder by 50% to 6-way. This is really a very big x86 core upgrade. Additionally, Intel for the first time since P6 (Pentium Pro) to SunnyCove is switching from L1-I cache fetching 16 Bytes per clock cycle to fetching 32 Bytes in GoldenCove. GoldenCove is the largest redevelopment and expansion since Conroe (Core2). SandyBridge wasn't that revolutionary.
I wish we knew a little more about this 6-way decode in Golden Cove. 3 simple plus 1 complex to 6... something? Why provide all of these details and then not detail the decoder? I guess they spent a lot of resources finding the optimum configuration and want to protect that intellectual property a bit longer?
With this, I agree that SandyBridge is revolutionary in these respects.
I was talking about pipelines and I consider the transition from the 4-way x86 to the 6-way decoder to be a revolution. It's not just adding resources. All the control logic and the algorithms contained in it have been completely redesigned or replaced with a new, more extensive one. You have a heavily rebuilt and expanded Front-End with a completely new predictor and preselector with new mechanisms. There have been big changes to the rest of the x86 core as well, but so far Intel hasn't revealed everything yet. The fact that GoldenCove basically uses similar mechanisms as SandyBridge does not mean that it is the same microarchitecture. With each generation, new mechanisms and algorithms are added to the x86 core to increase the IPC. In my opinion SunnyCove is the biggest change since SandyBridge and GodenCove is the biggest change since Conroe.
That's my opinion but you don't have to agree with it
I wish we knew a little more about this 6-way decode in Golden Cove. 3 simple plus 1 complex to 6... something? Why provide all of these details and then not detail the decoder? I guess they spent a lot of resources finding the optimum configuration and want to protect that intellectual property a bit longer?
They implemented a loop buffer, intel also had a loop buffer in Nehalem.I think the uOP cache alone was a massive upgrade in Sandy Bridge. AMD was at a serious disadvantage there. I think they tried some half assed solution around Steamroller but it wasn't really a thing until Zen.
6... something? I found that one funny, I guess because it's true. From what I understand the complex decoder is rarely used, so maybe 5 simple + 1 complex? Or maybe they went another way entirely?
Of course, the presentation doesn't talk much about the exact limits of decoding. They've often been much more complex than the ostensible "16B and 4-1-1-1", where the rules for what counts as "simple" can be quite surprising.
(For example, r-m-w instructions are exactly as simple as load-store instructions from a pure decoding angle, but count as complex because depending on the microarchitectural details they might end up being two uops).
I think the uOP cache alone was a massive upgrade in Sandy Bridge. AMD was at a serious disadvantage there. I think they tried some half assed solution around Steamroller but it wasn't really a thing until Zen.
Don't get me wrong I want to see what ADL can do, it looks rather potent. It probably will be the biggest upgrade since Sandy Bridge. Sandy Bridge though was lauded though and rightfully so. That became even more obvious after the Bulldozer disaster.
6... something? I found that one funny, I guess because it's true. From what I understand the complex decoder is rarely used, so maybe 5 simple + 1 complex? Or maybe they went another way entirely?
Of course, the presentation doesn't talk much about the exact limits of decoding. They've often been much more complex than the ostensible "16B and 4-1-1-1", where the rules for what counts as "simple" can be quite surprising.
(For example, r-m-w instructions are exactly as simple as load-store instructions from a pure decoding angle, but count as complex because depending on the microarchitectural details they might end up being two uops).
They implemented a loop buffer, intel also had a loop buffer in Nehalem.
anything that becomes more then 1 uop can't use the simple decodes, but even then there are more complex rules
These are good points. I'm actually quite curious how Atom team put everything into such a small area. Some parts of cores are even bigger than Golden Cove (L1 cache and issue ports) We already know that the Willow cove(which is almost the same as Sunny cove) core uses more than 10mm2 of die space. 2015 Skylake used 8mm2 of die space, it'll be 3~4mm2 with 10ESF assuming 50~70% of shrink. But Gracemont uses 1.5~2mm2. Surprising.
With this, I agree that SandyBridge is revolutionary in these respects.
So the performance cores are faster and the efficiency cores slower, but roughly the same as 16 zen3 in MT.
Honestly that bench shows almost no differences between a 8 core, 16 core and 24 core with different clocks and IPC. Whatever it measures it's moot if all current/next gen CPUs perform almost the same, I'd even take leaked Geekbench scores as more indicative than that suite.
Why is that a problem? If only everyone here would try to make educated guesses
One thing puzzles me and bothers me. According to Intel slides, GoldenCove has a 6-way x86 decoder while SunnyCove according to the same slide has a 4-way x86 decoder. Really strange because I thought that Skylake and SunnyCove have a 5-way decoder according to, among others, wikichip.
Your over selling intels decode, it has been 4+1+1+1 uop's with 16bytes from L1i where heaps of basic instructions cant be done by the simple units because they decode into 2 uops, compared to Zen which is 2+2+2+2 + mircocode engine with 32bytes from L1i.
They implemented a loop buffer, intel also had a loop buffer in Nehalem.
Honestly that bench shows almost no differences between a 8 core, 16 core and 24 core with different clocks and IPC. Whatever it measures it's moot if all current/next gen CPUs perform almost the same, I'd even take leaked Geekbench scores as more indicative than that suite.
Gracemont sounds to good to be true.
While it's an exaggeration of figures, if it runs hotter and uses more energy to maintain its clocks without throttling itself at stock or very likely in an OC'd state, then it is DOA to me. That's my personal take on Alderlake, and it shouldn't affect anyone else's personal opinion on what's acceptable and what isn't.Seriously, 200 watts more than 5900x? That is absurd.
This. The project is still in pathfinding and Jim Keller left Intel last year. MLID trying to clickbait. Glenn Hinton is the one working on it. The so called "exciting high performance CPU project" he mentioned in his LinkedIn post.
I'm starting to "get" the rationale behind ADL I think. 8 big, fast cores to compete with Zen 3 head-to-head against the 5800X. I know this is dangerous water I'm treading into but I think Intel is reasoning that *most* people don't really need more than 8 cores AND there is still a lot of software that doesn't scale in a linear fashion past 8 cores.
So adding the Gracemont cores solves quite a few "competition" problems:
1. They are small so no chiplets, dies can remain monolithic.
2. They are power efficient making them great for mobile and ultramobile. Now besides downclocking laptops with power settings, that slider bar can also move compute toward the Gracemont cores when on battery if needed.
3. The Gracemont cores allow for better competition with the 5900X and 5950X.
4. They allow for lots of mix and match options in the products stack.
5. Gracemont and Golden Cove can be independently "upgraded." That is the Cove can be enhanced on one generation, Mont on the next.
6. Two development teams might lead to a more flexible Intel, able to zig or zag as required.
First step is Lakefield. Not only building blocks rationale, but also actual stacked tiles. In the context of advanced design & packaging, Alder and Raptor are vestiges of the old way of doing chips at Intel.Alder Lake is the first iteration of the road to disaggregated tiles. You can see that with their "building blocks" rationale, even if their dies are monolithic.
Intuitive diagram drawn by Cardyak:
Of I'm not wrong, GoldenCove has at least ~25% more integer resources than Gracemont (5 ALU ports in GC compared to 4 in GM)
At least Gracemont contains some innacuracies like FP pipes being completely wrong. There are two "symmetric" pipes that can both do FADD and FMUL. As shown in that picture it would perform horribly with 1 throughput for critical operations.