That's because you're assuming that Intel Skylake and Coves are extremely well designed. But that's not the case. We already know that there are many different types of CPU microarchitecture that achieved much higher PPC/PPA. Zen 3 and Apple M1.
For example, Zen3 achieved more IPC than Sunny Cove while using 256 reorder buffer and 4 ALUs(Same as Gracemont ALU count). And still smaller than Tiger lake. TSMC 7nm and Intel 10SF isn't really same but they have similar density. This confirms that there are huge rooms to improve.
I'd bet that Atom team has achieved substantially more than the Cove team did. Intel wasn't really using their transistors well. It's more like Intel Cove was wasting "cakes".
Um… OK? Intel big core teams are not good? Tell me something I don’t know.
On the other hand, the same team that designed Tremont also designed Gracemont and you can do the Tremont/Skylake comparison with real silicon like I said. What makes you think they suddenly figured out how to get ~2x the peak perf without spending any more area in a single iteration? Pro-tip: they didn’t.
The small print states these are pre-silicon projections. I would not trust these values given last few years Intel implementation performance. Did this get measured in real silicon later?
Um… OK? Intel big core teams are not good? Tell me something I don’t know.
On the other hand, the same team that designed Tremont also designed Gracemont and you can do the Tremont/Skylake comparison with real silicon like I said. What makes you think they suddenly figured out how to get ~2x the peak perf without spending any more area in a single iteration? Pro-tip: they didn’t.
What's the comparison point and in what workload? Because if we're talking the 6700K (AKA 4GHz boost clock) in the right workloads each Gracemont core absolutely can just straight out-perform it on a per-core basis.That's not the point. In the second graph, you can see the performance of a big core extend much higher up the performance axis. That is how the graph is supposed to look.
But in the first graph, the e-core actually achieves higher overall performance than Skylake at any point you draw a vertical line. It even shows the Atom having a higher peak performance than Skylake where the graph terminates. That is pure nonsense. You don't get performance out of thin air without spending silicon area. The real graph needs to be extended way further to show that the Skylake still has a higher performance envelope, even if it uses higher power to do so.
Alternatively, you can believe that graph as is and conclude that 8+8 can beat 16 zen cores. Oh wait, that is what some people on this thread have concluded. LOL.
Also yeah in the right conditions ADL can beat a 5950X in MT. CB20 is one of those. That doesn't mean it will in every workload.
The small print states these are pre-silicon projections. I would not trust these values given last few years Intel implementation performance. Did this get measured in real silicon later?
Not that I've seen unfortunately. And again, it will depends on the workload - Cinebench R20 is a best case scenario.Is there a screenshot of the bench.?.
Because that would mean that a small core has way higher IPC than a Zen 3 core...
Because that would mean that a small core has way higher IPC than a Zen 3 core...
Not that I've seen unfortunately. And again, it will depends on the workload - Cinebench R20 is a best case scenario.
You mean the big core. The big core has higher IPC but the gap is probally more to the big core MT clocks. And of course 250 W versus... like 140?
For example, if we pick up Cinebench R20 single-core then we can find its single-core performance is 294
So, we found that Tremont IPC was somewhat between Haswell and Skylake
People are being sarcastic because this is turning into a hope and belief contest.I'm actually quite surprised to see people being sarcastic here. Lakefield was already announced 2 years ago and chips and benchmarks are everywhere. Maybe Intel is investing in the Internet itself to cover up all their failures of Tremont just to mess with me? Interesting...
8 big cores run at 5GHz, wich provide 25% frequency advantage over 8 Zen cores, and then there s 8 small cores that run at 4GHz and without SMT, you think that the big cores can compensate for such a discrepancy.?..
8 big cores run at 5GHz, wich provide 25% frequency advantage over 8 Zen cores, and then there s 8 small cores that run at 4GHz and without SMT, you think that the big cores can compensate for such a discrepancy.?..
Intel use the same benchmarks for every IPC figure they give. Same methodology, every time (kudos to them for it too).If Cinebench is a best case then no doubt that it would had been used by Intel in their average and displayed here :
Yet, it is not...
Haswell score at 3.3GHz is something like 310.
Cinebench R20: Benchmark-Ergebnisse mit AMD & Intel
Wie schnell ist welcher Prozessor im CPU-Benchmark Cinebench R20? Die Community hat hunderte Modelle von AMD und Intel im Vergleich.www.computerbase.de
Again, depends on the workload.
Intel use the same benchmarks for every IPC figure they give. Same methodology, every time (kudos to them for it too).
Even for GLC R20 is a best case scenario. ~25% uplift over Zen 3, almost 30% vs Rocket Lake. The 810 ST number is real as far as I know anyway.
Based on overall scores and individual subcomponent scores on: SYSmark 25, CrossMark, PCMark 10, SPEC CPU 2017, WebXPRT 3, Geekbench 5
If the IPC gain between Cypress Cove and Golden Cove is enough, possibly. Uzzi's right that it's more likely an outlier. Have to be 20% or more.
Cypress Cove does 6000 pts , with 20% more that s 7200, and then there are something like 4100 pts that should be produced by the small cores to get to the alleged 11300.
6+0+1 HP = 6 P-cores + GT1 graphics (Intel Family 6, Model 151, Stepping 5?)
Tremont and Sunny cove in Lakefield performance-power curve intersect at 55% of maximum sunny cove performance(which has +20% IPC compared to Skylake with better lithography).
Since Sunny cove in Lakefield is manufactured using intel 10nm, If you put a hypothetical Skylake curve there, it'll be well above Sunny cove since it's manufactured using 14nm and uses an old design and max boost clock is 3Ghz.
And we can put a hypothetical Gracemont core curve there, it'll be below Tremont since it uses better uArch and process(10ESF) compared to Tremont(Normal 10nm(not 10SF), which has a worse high voltage scaling). I don't think it's unrealistic. Tremont was already good enough, like 25% behind Skylake(And pretty sure max boost clock of Lakefield is from Sunny Cove so Tremont IPC must be quite high already).
So in short, Tremont was already good enough before, Intel called them 'Big-core level' and Tremont benchmark numbers are everywhere. And Gracemont should be better.
There's only one Rocket Lake die, 8+1 HP, and it's 276 mm² on 14nm. SKUs based on it retail between $157-$539. The ADL 6+0+1 HP die is intended to replace Comet Lake Refresh (CML 6+2), which fills in the entry level desktop SKUs between $64-$192. Intel needs an HP die that can be used for lower-cost LGA 1700 platforms. The ADL 6+0+1 die had a definite slot on the production dashboard earlier this year, and its corresponding CPUID, 90574 (Model 151, Stepping 4), has shown up in benchmarks as recently as last week.The 6+0 is gone. Replaced with Rocket Lake Refresh. Dunno if it's LGA 1700.
There's only one Rocket Lake die, 8+1 HP, and it's 276 mm² on 14nm. SKUs based on it retail between $157-$539. The ADL 6+0+1 HP die is intended to replace Comet Lake Refresh (CML 6+2), which fills in the entry level desktop SKUs between $64-$192. Intel needs an HP die that can be used for lower-cost LGA 1700 platforms. The ADL 6+0+1 die had a definite slot on the production dashboard earlier this year, and its corresponding CPUID, 90574 (Model 151, Stepping 4), has shown up in benchmarks as recently as last week.