IntelUser2000
Elite Member
- Oct 14, 2003
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Hmm, thought they used EMIB on one of the chip layers instead of stacking monolithic dice. Maybe I misinterpreted their presentation.
The die size is 60-70mm2 at most. Yes they stack the 10nm CPU/GPU die on top of the 22FFL process die which includes all the chipset functions.
Isn't latency also in play here? Though nobody's said anything about how EMIB connections affect latency versus "traditional" MCM configurations. At least not that I've seen.
If you look at package shots for Icelake, the two chips are extremely close, and it uses OPIO. You can also compare that to Kaby-G, which uses EMIB.