SMT at the very best is 1.3x, often it is 1.1x to 1.2x, rarely it is 0.9x to 1.0x.
SMT at the very best is 1.3x, often it is 1.1x to 1.2x, rarely it is 0.9x to 1.0x.There s SMT to consider at 1.3x.
He' saying that the >50% is referring to the performance of Gracemont core espect to the Golden Cove core (and you can see indeed on the graph that the Gracemont is around half the performance of Golden Cove). If you calculate instead how much the Golden cove is more powerful respect to the Gracemont, you have to do the inverse ratio, that is around 100% more performance for Golden Cove if the baseline is Gracemont.
It can't be right, or Intel is in (more) serious trouble. Those are just measurements based on renders which probably aren't exact representations of the actual products.that does not sound right. TGL 4+2 is estimated to be 146mm2. ADL 2+8+2 is replacing 2 big cores with 8 small ones. the general consensus has been 4 small cores are the same size as one big one. So die size should be the similar between TGL 4+2 and ADL 2+8+2. While cove may have increased in size, ADL is also using a newer process.
Charlie estiamted TGL 8+2 as 237mm2. Intel is doing a similar replacement here too. I just don't see die sizes increasing by 30-40%.
Tiger Lake 4+2 LP die is 13.6 mm x 10.7 mm = 145.5 mm².
Tiger Lake 8+1 HP die is 18.9 mm x 10.5 mm = 198.5 mm².
View attachment 49202
No attempts at performance or efficiency estimates should be made from these graphs, just like all the other worthless graphs Intel has been putting out lately.
It isn’t correct at all. Two different architectures in 2 different processes. Sapphire Rapids is said to be around 400 mm2 for a single tile for reference.It can't be right, or Intel is in (more) serious trouble. Those are just measurements based on renders which probably aren't exact representations of the actual products.
There is no TGL 8+2 (I'm guessing you meant 8+1), but there's also no need to estimate TGL die sizes anymore seeing as they're in the wild and we can measure them. As I posted previously:
Ah well, I agree with you, only the reviews will give us an answer about that.
Seriously this.View attachment 49202
No attempts at performance or efficiency estimates should be made from these graphs, just like all the other worthless graphs Intel has been putting out lately.
SMT at the very best is 1.3x, often it is 1.1x to 1.2x, rarely it is 0.9x to 1.0x.
Perhaps some of the subtlety was lost along the way here, but naukkis claimed that we had some idea of the ADL 8+8+1 die size. I responded that AFAIK, there are no publicly available die or wafer shots of ADL yet, so we really don't know where they'll land in terms of die size. naukkis then offered the Architecture Day 2021 presentation materials as a possible way to estimate die size. Intel did provide us with the exact package dimensions as well as package renders, so I went ahead and measured the "dies" in the renders. I'm pretty sure my measurements of said "dies" are correct, but the results, taken in context, would appear to be nonsense.It isn’t correct at all. Two different architectures in 2 different processes. Sapphire Rapids is said to be around 400 mm2 for a single tile for reference.
I am thinking die sizes will be similar to rocket lake. The GPU will use less space, the cores will be slightly larger. The largest sku would be roughly the same size as 10 golden cove cores.
Sapphire Rapids XCC 15C tile is exactly 426.4 mm².
Just judging by my common sense and educated-as-can-be guessing. I don't know, heck, I can't knowAny indication of that?
OK, we do know the package dimensions, so I went ahead and measured these renders from the Architecture Day presentation (which are probably not all that accurate, mind you).
View attachment 49198View attachment 49200View attachment 49201
Which gives us the following:
ADL 2+8+2 LP: 18.4 mm x 11.2 mm = 206 mm².
(For reference, CML 10+2 HP is 22.4 mm x 9.2 mm = 206 mm².)
ADL 8+8+1 HP: 25.2 mm x 12.6 mm = 318 mm².
(For reference, RKL 8+1 HP is 24.0 mm x 11.5 mm = 276 mm².)
And wait for it... ADL 6+8+2 LP: 29.8 mm x 14.6 mm = 435 mm².
(For reference, SPR 15C tile is 20.8 mm x 20.5 mm = 426 mm².)
There is no way Intel can maintain anything like their traditional margins with 10nm client dies that size.
You're right. Things most of us deem silly or improbable never happen.That's silly. When has Apple ever shown it can successfully sell to enterprises? The sales it makes to businesses now (which are mostly to smaller/mid sized businesses not Fortune 500 sized companies) are almost an afterthought, they make those sales without really trying or appearing to care that much.
Entering the server market would be a huge departure for them, and even if they totally dominated on benchmarks that wouldn't be any guarantee of success as people making those purchase decisions value vendor support (and knowing that vendor support will still be as good five years down the road as it is on day one) more than anything else. There's a reason why when AMD started beating Intel with Opteron and more recently with Epyc it took a couple years before that started having any real impact on market share. Enterprise buyers are conservative by nature, the "nobody ever got fired for buying IBM" saw is kind of true - it is a bigger risk to say "let's go a different way this time" so most will want to have seen others successfully take that risk before they will jump.
If Apple repurposes the "Jade-C" building blocks for their higher end into server CPUs I bet it would be for internal use only. Maybe after a few years of using it successfully internally they might think about productizing it, but I'm skeptical. One of the reasons they've been so successful is that they focus on a few fairly narrowly defined markets, and are almost entirely consumer focused. Consider that the entire worldwide server market (from OEMs so counting everything from RAM to storage to racks and so on, way more than just CPUs) is a bit less than $100 billion a year. They'd need to take 20-25% of that market just to equal what they make from Airpods! So it isn't like they'd be able to have a big impact on the overall business with even the rosiest possible outcome.
View attachment 49202
No attempts at performance or efficiency estimates should be made from these graphs, just like all the other worthless graphs Intel has been putting out lately.
Heh. Look at these two, they literally just contradicted themselves with the two curves on ST power/perf between the two cores.
Er... one is comparing Skylake and the other Golden Cove.
But in the first graph, the e-core actually achieves higher overall performance than Skylake at any point you draw a vertical line. It even shows the Atom having a higher peak performance than Skylake where the graph terminates. That is pure nonsense. You don't get performance out of thin air without spending silicon area. The real graph needs to be extended way further to show that the Skylake still has a higher performance envelope, even if it uses higher power to do so.
That's not the point. In the second graph, you can see the performance of a big core extend much higher up the performance axis. That is how the graph is supposed to look.
But in the first graph, the e-core actually achieves higher overall performance than Skylake at any point you draw a vertical line. It even shows the Atom having a higher peak performance than Skylake where the graph terminates. That is pure nonsense. You don't get performance out of thin air without spending silicon area. The real graph needs to be extended way further to show that the Skylake still has a higher performance envelope, even if it uses higher power to do so.
Alternatively, you can believe that graph as is and conclude that 8+8 can beat 16 zen cores. Oh wait, that is what some people on this thread have concluded. LOL.
But in the first graph, the e-core actually achieves higher overall performance than Skylake at any point you draw a vertical line. It even shows the Atom having a higher peak performance than Skylake where the graph terminates. That is pure nonsense.
I agree. These graphs are BS even if the performance turns out not to be. When I was an engineering student if I submitted graphs like these, with no values/units on the x and y axis, my professors would have immediately failed me. If the performance/efficiency is so great just show actual graphs with actual data points. Those graphs would speak for themselves.
Why is it pure nonsense? We're comparing 14nm manufactured + 5 years ago architecture with 10nm(Intel 7) + brand new microarchitecture. Do you mean that Atom cannot surpass 'any' big cores, like Ivy Bridge, Haswell, Broadwell...?
21st-century family cars can easily win against 60 years ago muscle cars in any environment. 5 years is quite a long time.
Why is it pure nonsense? We're comparing 14nm manufactured + 5 years ago architecture with 10nm(Intel 7) + brand new microarchitecture. Do you mean that Atom cannot surpass 'any' big cores, like Ivy Bridge, Haswell, Broadwell...?
21st-century family cars can easily win against 60 years ago muscle cars in any environment. 5 years is quite a long time.
It is nonsense because that massive of an increase in performance per area would be the engineering equivalent of having a cake after eating it ten times over.
Skylake shrunk to 10ESF wouldn't be that outrageously bigger than Gracemont. Even without any sort of optimization for density over mhz.
It is nonsense because that massive of an increase in performance per area would be the engineering equivalent of having a cake after eating it ten times over.
Just go compare the performance peak of Tremont (which is not 5 years old) compared to Skylake and see how absurd the leap would have to be for that first graph to be believed as a generic statement.