RE: Intel 4/3 transistor density discussion
The goal of this post is to find out what density Intel 3 could achieve.
[TLDR]
Although at first sight I, too,
was disappointed by Intel 4, more careful analysis has shown that Intel should readily be able to achieve its 2x density target for Intel 3, even on the HD library.
Hint: the key to the Moore's Law kingdom during the FinFET era has been fin depopulation, fin depopulation and even more fin depopulation.
Intel 3 could finally achieve what was deemed unthinkable: the holy grail single fin transistor cell.
[clarification/obfuscation]
Intel has made two separate claims for Intel 3:
1. "Denser HP library" -> likely using the increased performance of Intel 3 for fin depopulation and/or using the increased EUV usage to reduce some pitches
2. "Higher performance library" -> this is the wording in the Investor Meeting presentation on the slide, but Ann said "with the addition of a denser HP library"
Since 10nm has 3 libraries (short/mid/tall) and Intel 4 has only the tall library, the introduction of an even "higher performance" library seems unlikely. More likely, Intel could have meant that the performance of the HP (tall cell) library will be higher due to the increased drive current in Intel 3.
Note that the claim of higher performance makes fin depopulation unlikely, so this implies that Intel 3 uses more EUV not just to replace SADP layers, but also for pitch reduction, although this seems quite exceptional for an intra-node, unless Intel on purpose is positioning Intel 3 as a half-node to compete more effectively against TSMC N3.
[clarification/obfuscation 2]
The Intel 4 presentation shows how the HP library goes from 4+4 fins per cell to 3+3 fins per cell. However, WikiChip showed in 2018 how the 408nm cell actually has room for 4+5 fins:
https://fuse.wikichip.org/news/2004...m-standard-cell-library-and-power-delivery/3/.
[observation]
Going from 4+5 fins per CMOS to 3+3 fins per CMOS from 10nm to Intel 4 is quite impressive and is a testament to the performance improvements Intel has delivered from 10nm+ (Ice Lake) to Intel 3. By my calculation performance is increased by nearly 2x (despite the 1.5x fin depopulation): 1.18 (10SF) * 1.15 (7) * 1.21 (4) * 1.18 (3) = 1.94. This implies performance per fin has increased by around 3x in just one full node (albeit many intra-nodes).
Adding this all up, Intel 4 HP library achieves a 1.5x reduction in fin count (going from 4+5 to 3+3) compared to Intel 7 while simultaneously delivering 1.21x performance. Intel 3 will add a further 1.18x performance.
[extrapolation]
By using the observation above, one can now extrapolate how many fins Intel would need in the Intel 3 library in order to maintain the same performance as 10SF or Intel 7.
Intel 7: HD library has 5 fins -> reduce by 1.5x due to fin depopulation -> Intel 4 still delivers 1.21x performance (-> Intel 7 improves performance by 1.15x) -> Intel 3 delivers 1.18x performance -> results in 2.3 (2) fins per transistor.
In other words, this calculation shows that a 2-fin Intel 3 cell could have the same performance as a 5-fin 10nm SuperFin cell.
[scenario 1]
According to my analysis, assuming no changes in pitches from 4->3, Intel 3 HD library ("Intel 4 HD library") will have a density of either 160MTr/mm2 (2+2 fins), 200MT (1+2 fins) or 240MTx (1+1 fins).
Note that (as mentioned) compared to Ice Lake 10nm, Intel 3 will have almost 2x performance (1.18*1.15*1.21*1.18), so a 1+2 or even 1+1 single fin configuration doesn't seem as crazy as it might first sound. Intel is squeezing every bit of performance out of their last FinFET node.
[scenario 2]
Intel 3 is definitely *not* just the Intel 4 HD lib since Intel claims +18% perf. In addition, as Exist50 remarked (and as discussed), Intel said Intel 3 will have denser HP libraries. This means there must be some changes in pitches and/or fin depopulation.
In the case of denser pitches (which could be possible given the increased use of EUV), these pitches will also affect the HD library obviously, so the the density values above should be regarded as worst-case.
In the case of fin depopulation, then likewise it makes sense for the HD library to follow suite, favoring the 1/2 or 1/1 configurations that deliver at least 200MT density, accomplishing the 2x jump in density.
[conclusion]
Intel has previously changed pitches in its intra-nodes, at both 14nm and 10nm, but that always consisted of actually *reducing* the gate pitch. As such, on first sight it might seem most obvious that Intel would do further fin depopulation in Intel 3 HP library. However, Intel said that the library would be both denser and higher performing. This suggests that the increased EUV usage might be used for some pitch reduction, making Intel 3 more of a half-node than an intra-node.
Nevertheless, Intel did disclose that it still uses SAQP on the M0 layer, and perhaps some SADP, which provides at least one opportunity to increase EUV usage. As mentioned there is ultimately no tangible evidence yet that Intel 3 is a half-node (pitch changes) rather than an intra-node.
In any case, the most amazing observation is that Intel has doubled or even tripled performance (per fin) in just one full node generation (10nm->7nm), albeit via many intra-nodes. This lends credence to the introduction of a 1+2 or even 1+1 fin HD library, achieving respectively a 2x or up to 2.4x improvement in transistor density.
While a 1+1 fin library seems incredible (coming from a 2+3 library), I wouldn't yet rule it out given the 2.4x density claim by BK in 2018. In addition, going from a 4+5 (9 fin) to 3+3 (6 fin) library from Intel 7 to Intel 4 already shows that Intel can do both fin depopulation as well achieve its performance targets simultaneously.
@repoman27 @JasonLD @IntelUser2000 @Ajay @JoeRambo @DisEnchantment @Exist50