I've often wondered just how much opportunity is even out there for ISA-based performance improvements to IPC. After tweaking on x86 for what now, 40yrs?
Is there much left to improve upon (in the ISA itself) or is it really the microarchitecture that delivers the performance/watt and IPC improvements here out?
Well, thats where AMD going with Fusion. But right now it seems AMD has the lead in Compute FP power and I dont see Haswell to be able to change that with AVX only.
Apples and Oranges. Thats like saying Nvidia GTX580 has the lead in Compute FP power over Intel SB. No kidding, different products.
Haswell will be an APU chip much like Llano, Trinity and the future Fusion chip from AMD in 2013.
Yes, some Haswell models will be an APU chip like Llano. But you are comparing Haswell's CPU FP performance to Llano's GPU FP performance. No one has any idea how well Haswell's GPU will perform in Compute FP. Sticking to the CPU side, I do not think any chip will match Haswell. However, on the GPU side (I can guess), that Trinity may be superior. But I still think your comparison is unfair and somewhat skewed, based on what we know today.
Indeed, but what's your point? Physical register files are more about reducing power consumption than anything else. How does it relate to the discussion of increasing throughput?But Nehalem doesn't
Why would Intel reduce it in any way? They've got a good architecture to build on. I'm not expecting them to radically change anything that would jeopardize IPC. They are more likely to make incremental changes, like extending macro-op fusion to create 3-operand instructions.What I means is just even we can't improve it, we should think of ways to not to reduce it a lot...
Yes, there are two 128-bit "lanes" which perform the same operation, so SSE instructions use only the lower half.Isn't Intel's AVX unit made by 2 128 unit, means legacy code can be also supported?
Yes, FMA+ADD is probably a better alternative than FMA+MUL. I've done a bit of research and found some interesting data in Figure 3 (a) and Table 1 of this paper: Latency Sensitive FMA Design. The average instruction mix contains 10.7% FMA, 12.5% ADD and 7.7% MUL. So if 100 instructions consisted of this distribution it would take FMA+FMA units 15.45 cycles, FMA+ADD units 18.4 cycles, and FMA+MUL units 23.2 cycles to execute the floating-point instructions. Note that this assumes there are no dependencies between them, which is obviously wrong. But note that in practice with dependencies FMA+FMA units would perform better than the alternatives because there are more combinations of instructions that can execute simultaneously. Furthermore this paper shows it's highly application-specific. For instance 173.applu, which is a physics application, would theoretically execute the floating-point instructions 50% faster on FMA+MUL versus FMA+ADD, and about the same on FMA+FMA (again, only in theory). FMA+FMA also runs ADD-heavy cases optimally while FMA+MUL would not. So which ever asymmetric design you choose a significant number of applications won't benefit.BTW, there is another opinion
"Anyway my opinion is that the optimal design choice is probably FMA+ADD. This is not just for power/cost reasons but also performance: a FMA unit will have very similar latency for MUL but significantly higher latency for ADD than a standalone unit. AMD had to compromise ADD latency on Bulldozer which doesn't seem ideal to me at this point in time."
Perhaps Haswell's CPU FP units will have higher compute power than AMDs, but i believe that it will not be enough to compete against future Bulldozer based + GCN APUs.
Again, you are not taking into account the compute power of the Haswell IGP, which is an unknown at this point. That coupled with the new Haswell instructions, should put up some decent numbers.
We will get some idea of how well (or poor) Intel's IGP can handle Compute FP with IB in a few months. IB will be the first Intel to support OpenCL.
We'd get a mixed bag if they go for an FMA+ADD or FMA+MUL configuration, which is sometimes slower than what we have today (see my previous post).Crap, you mean we aren't going to get something for nothing after all?
Both. On the ISA side there's AVX2 and BMI1/2 that will have a significant impact on some software, but will require a recompile. That's stuff that's currently on the roadmap. Going forward we should expect to see AVX-1024 reduce the power consumption of the front-end while also offering latency hiding.I've often wondered just how much opportunity is even out there for ISA-based performance improvements to IPC. After tweaking on x86 for what now, 40yrs?
Is there much left to improve upon (in the ISA itself) or is it really the microarchitecture that delivers the performance/watt and IPC improvements here out?
A penny for your thoughts.Oh there's definitely good stuff left.
ummmm....
I dont think so...
If you want to talk about ram speed... DDR3-2100 was possible on LGA1366.
If you ask me... the idiot at intel wanted a different look on intel a platform vs AMD because AMD started copying names off intel.
Are you the only one that knows what i mean? Did i not make sense?
Incase u guys didnt know... sandy-e has ram slots sandwitching the cpu.
Now tell me was there really truely a reason to stack the ram modules next to the cpu socket?
Is someone really going to tell me it made a revolutionized difference in how the cpu accepts ram?
no im talking about the physical ram layout of the board...
Do you know how tough that makes use having to cool stuff down? Also the limitations of the mosfets which can be fitted on the board?
True i know we never needed that many mosfets but... it makes the mosffet placement more staggard, and makes cooling it more difficult..
Im taking both CPU and iGPU compute power in consideration, im just saying that, even if Haswells CPU FP unit is much faster than AMDs, it will not be enough to counter the much faster iGPU unit in future Fusion GCN APU.
A penny for your thoughts.
Im taking both CPU and iGPU compute power in consideration, im just saying that, even if Haswells CPU FP unit is much faster than AMDs, it will not be enough to counter the much faster iGPU unit in future Fusion GCN APU.
That's only a measly 14% bandwidth increase for Trinity. To put things in perspective; the transistor count still doubles every two years.Llano uses 1866MHz, Trinity will use 2133MHz. Memory prices drops every year and memory speed rises too. 2013-2014 will see the introduction of DDR-4 and perhaps Haswell will utilize a DDR-4 memory controller too.
Too bad they won't be able to use half of that power because there's no bandwidth for it.Well, Llano has 480GFOPs in 2011, Trinity will have 50% more compute power in 2012 and next gen AMD Fusion chip in 22nm SOI HKMG in 2013 will probably have double Trinities Compute power (GCN). That is only the compute from the iGPU ALU units, add to that the CPU FP units as well and AMDs 22nm APUs with GCN will be a beast in FP compute power.
You can always pitch your idea on the Intel forum. Keep in mind that it has to have a good cost/gain ratio though, and not stand in the way of future development.For another example, I know what I just implemented would be speed up a lot by a little bit of content-addressable memory.
Indeed, but what's your point? Physical register files are more about reducing power consumption than anything else. How does it relate to the discussion of increasing throughput?
It sounds like if they widen the vector unit and we do not take 22nm into account, they'll reduce it by increasing the power.Why would Intel reduce it in any way? They've got a good architecture to build on. I'm not expecting them to radically change anything that would jeopardize IPC. They are more likely to make incremental changes, like extending macro-op fusion to create 3-operand instructions.
Ops, I don't know that.Yes, there are two 128-bit "lanes" which perform the same operation, so SSE instructions use only the lower half.
But as TuxDave already indicated that's not what I meant. Not having two FMA units will result in no performance gain for older code which only contains MUL and ADD instructions (and for numerical consistency reasons even new code may opt not to use FMA since it rounds the result differently). So there's good incentive for Intel to not promote one unit to FMA, but both.
Also note that even with one FMA unit and 256-bit integer operations they are forced to double the cache bandwidth(s). Without it there would hardly be any gains. But it would be a shame to still only partially take advantage of that extra bandwidth with a crippled floating-point implementation. I really don't see why on a 22 nm process they would hold back and make damaging compromises like that.
But the solution is AVX2. It doubles the integer and floating-point vector performance, brings us gather support for parallel memory accesses, and all of this is unified into the CPU cores. So the heterogeneous communication overhead is eliminated, out-of-order execution allows to achieve higher instruction-level parallelism so less data-level parallelism is required and hence it suffers less from Amdahl's Law, and it also handles register pressure more elegantly and there's better cache hit rates so it requires less RAM bandwidth.
not only, there is also a scalar variant of most instructions, for example when recompiling code for AVX2 targets scalar FMA instructions are used (in non-vectorizable routines)AVX is a SIMD instruction
yes but only if there is indeed 2 FMA units per core, otherwise FMA allows for more efficient code with less register fills/spills thus less pressure on the L1D cache. Note that current AVX already need more bandwidth to reach its full potential, the SSE/AVX-128 to AVX-256 speedups are quite deceptive on Sandy Bridge due to the lackluster L1D and L2/LLC bandwidth, I hope that Ivy Bridge will improve the situation, the remark for the 1.25x speedup in Excell 2010 in the leaked IVB benches http://www.tomshardware.com/gallery/intel_ivy_bridge_performance_1,0101-317230-0-2-3-0-jpg-.html makes me think there is some strong L1D and/or L2 bandwidth enhancementsAVX2 will need more memory bandwidth (cache or system)
why do you think Haswell will have a larger register file ?and because of its larger register files
Going forward we should expect to see AVX-1024 reduce the power consumption of the front-end while also offering latency hiding.
Haswell is all about AVX2. Its key feature is 'gather' support, which in some cases enables an eightfold increase in performance.
And...I'd like to ask is there any information about the percentage of the use of MUL, ADD and MAD in most software?