I think you've forgotten just how much faster Nehalem was over Penryn. The performance increase was around 20% at the same clock frequency, often more. Then came Sandy Bridge, enhancing performance by another 15% over Nehalem at the same clock. In my opinion, there's little reason to expect less than a 15% improvement from Haswell. Anything else would go against the trend that we've witnessed since the release of Core 2, when Intel introduced their "Tick-Tock" strategy.Except for P4 to Conroe I don't think there has been a new chip that has shown greater than 10% or so IPC increase. Keep in mind ALSO EXCEPT for new instructions that greatly speed up applications specifically coded for those new instructions. ie SSE for video editing.
So 5 to 10% IPC increase for a new part, plus a cooler faster running part, and some new instructions is a fine upgrade IMO.
I think you've forgotten just how much faster Nehalem was over Penryn. The performance increase was around 20% at the same clock frequency, often more. Then came Sandy Bridge, enhancing performance by another 15% over Nehalem at the same clock. In my opinion, there's little reason to expect less than a 15% improvement from Haswell. Anything else would go against the trend that we've witnessed since the release of Core 2, when Intel introduced their "Tick-Tock" strategy.
I think you've forgotten just how much faster Nehalem was over Penryn. The performance increase was around 20% at the same clock frequency, often more. Then came Sandy Bridge, enhancing performance by another 15% over Nehalem at the same clock. In my opinion, there's little reason to expect less than a 15% improvement from Haswell. Anything else would go against the trend that we've witnessed since the release of Core 2, when Intel introduced their "Tick-Tock" strategy.
EDIT: Just to clarify: As far as I know, most of these improvements were not because of new instructions.
With "new instructions" I was referring to instruction set extensions, such as AVX. Using IPC as a performance measure only works if the same instructions are executed. New instructions can for example mean that a new CPU gets a lower IPC for a particular workload but still provides higher performance.Care to elaborate on that last point? Other than IPC, where would the performance increase come from?
I think you've forgotten just how much faster Nehalem was over Penryn. The performance increase was around 20% at the same clock frequency, often more. Then came Sandy Bridge, enhancing performance by another 15% over Nehalem at the same clock.
.......Or the increase in TDP will come primarily from extra IGP.
Also i hope the idiot that though of sandwitching the ram between the CPU got fired and haswell doesnt go this model.
I really DONT like sandy-E's layout... actually i hate it with a passion.
With "new instructions" I was referring to instruction set extensions, such as AVX. Using IPC as a performance measure only works if the same instructions are executed. New instructions can for example mean that a new CPU gets a lower IPC for a particular workload but still provides higher performance.
If you want products that are born from engineers making performance-impacting compromises then you should get yourself an Interlagos.
Aha. Thank you for clarifying. But I wonder, why do people say IPC is 15% higher on X architecture than Y architecture if so?
Sorry I'm asking so many questions
In truth, IPC has a specific meaning in computer science but that meaning is heavily extended in its application at the laymen level of discourse with which we all engage here.
We tend to refer to changes in clock-normalized benchmark performance as being tantamount to a change in IPC.
But no benchmark app is strictly a single instruction exectuted multiple times. Benchmarks represent a collection of instructions, and the performance is more akin a that of a weighted average of that basket of instructions.
And there are a lot of instructions to consider:
No one here really delves into the contents of the basket (is it 50 instructions? 25? 100? in the bench) nor the weighting (is FDIV called 50 times while MUL is called 10 times?).
So what do we mean when we say "15% IPC increase"? The spirit of what we are referring to is the generalized improvement in benchmark performance on a clock-normalized and core-normalized basis. (same clockspeed, same core count, typically single threaded)
Also i hope the idiot that though of sandwitching the ram between the CPU got fired and haswell doesnt go this model.
By "sandwiching RAM between CPU" you are referring to technologies like on-package or stacked memory right?
Aigo just said the guys trying to achieve that are idiots. Tell me I'm wrong and he's not talking about on-package/stacked memory.
Think he means the DDR slot layout on the mainboard, having DDR slots on either side of the CPU socket.
No one here really delves into the contents of the basket (is it 50 instructions? 25? 100? in the bench) nor the weighting (is FDIV called 50 times while MUL is called 10 times?).
That team of "idiots" probably got you a platform that could run DDR3-1600 or 1866 stably, versus running longer traces and you only getting DDR3-1333 (or slower) speeds...or the alternative of making miracles happen at the expense of bringing a mobo to market that costs $2k.
Think he means the DDR slot layout on the mainboard, having DDR slots on either side of the CPU socket.
By "sandwiching RAM between CPU" you are referring to technologies like on-package or stacked memory right?
Aigo just said the guys trying to achieve that are idiots. Tell me I'm wrong and he's not talking about on-package/stacked memory.
no im talking about the physical ram layout of the board...
It seems like useful to us to delve into it, I know some fans are trying to do so.In truth, IPC has a specific meaning in computer science but that meaning is heavily extended in its application at the laymen level of discourse with which we all engage here.
We tend to refer to changes in clock-normalized benchmark performance as being tantamount to a change in IPC.
But no benchmark app is strictly a single instruction exectuted multiple times. Benchmarks represent a collection of instructions, and the performance is more akin a that of a weighted average of that basket of instructions.
And there are a lot of instructions to consider:
No one here really delves into the contents of the basket (is it 50 instructions? 25? 100? in the bench) nor the weighting (is FDIV called 50 times while MUL is called 10 times?).
So what do we mean when we say "15% IPC increase"? The spirit of what we are referring to is the generalized improvement in benchmark performance on a clock-normalized and core-normalized basis. (same clockspeed, same core count, typically single threaded)