Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Hulk]

That was the goal but there’s 2 snags.

1) MTL was late. It was supposed to launch shortly after Phoenix.
2) ARL reuses MTL packaging. All of the negatives of that cursed tiled setup is inherited by ARL. The only kind of saving grace is that ARL-S has an SoC tile that’s more favorable to desktop but It’s still less than ideal.

It’s not a coincidence that LNL & PTL are dropping that packaging for a simpler implementation.

True but the positives of the tiled setup remain as well. Smaller dies=higher yields, varied nodes=better economics, plus the ability to only change part of the complex.
I'm not arguing for or against but AMD has it working beautifully. Perhaps will do better with ARL? We shall see.

 

[Gzxy]

True but the positives of the tiled setup remain as well. Smaller dies=higher yields, varied nodes=better economics, plus the ability to only change part of the complex.
I'm not arguing for or against but AMD has it working beautifully. Perhaps will do better with ARL? We shall see.

True but you have to include packaging cost. Yields? Intel7 must be yielding insanely good the last years so MTL didn't help with yields. Maybe it even resulted to worse yields since Intel4 is a newer node. ARL, Granite Rapids and Battlemage will play a big role for Intel in the next years. They cant afford to continue releasing lackluster products and losing market share. Also Falcon Shores will be essential for their AI revenue. Right now they are 1+ gen behind in data center AI GPUs / Accelerators or whatever you wanna call these products.

 

[DavidC1]

That was the goal but there’s 2 snags.

1) MTL was late. It was supposed to launch shortly after Phoenix.
2) ARL reuses MTL packaging. All of the negatives of that cursed tiled setup is inherited by ARL. The only kind of saving grace is that ARL-S has an SoC tile that’s more favorable to desktop but It’s still less than ideal.

Meteorlake was supposed to launch instead of Raptorlake. That is 2022! The timeline you are thinking about(H1 2023) is the delayed version.

It may not be the most optimal, but there's still plenty of chances and low-level details they can make that'll improve the "cursed tile" issue as you and others are calling it. Idea is important, but it's also very important to successfully execute on that idea, since in theory, Foveros and tiles are supposed to be superior over the approach AMD uses.

Go back on some earlier Meteorlake slides. Making the losses of moving to Tiles irrelevant was their goal. They definitely missed many of the low-level targets they were originally planning.

True but you have to include packaging cost. Yields? Intel7 must be yielding insanely good the last years so MTL didn't help with yields. Maybe it even resulted to worse yields since Intel4 is a newer node.

There are three types of yields:
1. How many dies you can get out of the wafer? A 100mm2 die allows you to make more than double the 200mm2 dies, because a larger die has more of the portion of the wafers lost. This is assuming zero silicon defects.
2. Does it have defects on silicon? Defects on silicon(which are random) can further reduce the amount of dies you can get out of the wafer. While Intel 7 may be mature and have extremely low silicon defect rate, the die being bigger means you have more of the wafers being wasted. Smaller dies also have less chance of a defect disabling a critical portion that renders it useless compared to a larger one.
3. Parametric yield: Cannonlake may have had low silicon-level defect but it's not enough. You need to have it perform. The parametrics, or the performance of the silicon matters. What would you take? A 10% faster one with 20% defects or one without the defects but without the 10% advantage? The 10% advantage can easily make up for the silicon loss by allowing it to be sold for higher cost.

Do not overestimate the cost of the silicon. For small die parts such as Intel's Core i3 and below line, the costs of the packaging is similar to the cost of the die. It was something like $5+$5. So in such a case, it's not really advantageous to get to a smaller die, because it's a small portion of the total cost.

 

[jpiniero]

Have to say, I am seeing a lot more Meteor Lake than I would have expected. Granted, AI AI AI, so maybe not?

Lenovo even has a section on "AI Gaming PCs"

 

[Hulk]

SOT but considering all of this AI coming to CPU's I keep having this nagging feeling that AI might be more server based rather than client.
Am I way off base here in thinking this?

 

[jpiniero]

SOT but considering all of this AI coming to CPU's I keep having this nagging feeling that AI might be more server based rather than client.
Am I way off base here in thinking this?

It's mostly marketing to Wall Street.

 

[LightningZ71]

It's like ray tracing in GPUs... There is actual AI capability there, but it's highly limited in what it can accomplish locally in a timely fashion. You can run huge models on it, but it'll take forever. You can do smaller local tasks and they will be performant. However, the difference is that, with a subscription and remote service, you can access the capabilities of a bigger AI cluster located in a DC elsewhere.

 

[Gideon]

Anything new people care to extract from this image?

https://twitter.com/x/status/1795763449425010756

 

[Kepler_L2]

Anything new people care to extract from this image?

https://twitter.com/x/status/1795763449425010756

Looks similar to previous schizo diagram by @AMDK11

 

[poke01]

https://twitter.com/x/status/1796118604133421387

I don’t know what to make of this

 

[CouncilorIrissa]

https://twitter.com/x/status/1796118604133421387

I don’t know what to make of this

Sounds exciting, if true.
I wonder how these changes will affect the area, though. Doubling the ALU count and increasing decode width by 50% can't be cheap area-wise?

 

[Philste]

Sounds exciting, if true.
I wonder how these changes will affect the area, though. Doubling the ALU count and increasing decode width by 50% can't be cheap area-wise?

The official graphics of Lunar Lake (given they show the real scale) already show that 4 Skymont are definitely bigger than 1 Lion Cove, so the 1/4 the size of a P-Core definitely isn't true anymore.

 

[eek2121]

Sounds exciting, if true.
I wonder how these changes will affect the area, though. Doubling the ALU count and increasing decode width by 50% can't be cheap area-wise?

Intel is using a more efficient process which will help, but yes, the cores are bigger. They will also be much faster.

 

[csbin]

Sounds exciting, if true.
I wonder how these changes will affect the area, though. Doubling the ALU count and increasing decode width by 50% can't be cheap area-wise?

true

https://twitter.com/x/status/1796139006675103896

 

[poke01]

let’s see lion cove at computex.

 

[DavidC1]

I don’t know what to make of this

Wow! This is exciting.

What I can make out:
-Flexible & Scalable: Shows Lunarlake and Arrowlake
-Increased IPC Gains: Left is likely Int and right is FP. FP gains are greater. Integer gains seem to be not 1.1n x but 1.2n x or 1.3n x.
-Two graphs of "something" Power and Performance compared to another core. Guessing one is for performance and other is for power(Arrowlake and Lunarlake). For the Performance graph it shows 2x performance with more power. At the same power it seems to be showing 1.5 or 1.7x. It also seems to say "1/3 power" at same performance. The low power graph shows massive gains(2.4x at the same power?), probably compared to Crestmont LP? Scales to 4x or 5x compared to Crestmont LP at higher power.
-Skymont uArch Goals
-"something" Decode: 9-wide(3x3), "Nanocache"?
-"something" Predict: 128 bytes, Faster
-"something" OoOE Engine: 8-wide and 16-wide, Dependency "streaming"?
-Deeper Queueing with More Resources

I said it before and I'm calling it now. 10% faster in Int and little bit behind FP compared to Golden Cove.

 

[Kepler_L2]

Sounds exciting, if true.
I wonder how these changes will affect the area, though. Doubling the ALU count and increasing decode width by 50% can't be cheap area-wise?

Skymont is same area as Gracemont despite 2 node shrinks. So a lot more transistors.

 

[AMDK11]

Looks similar to previous schizo diagram by @AMDK11 View attachment 99896

I won't be surprised if LionCove has more than an 8-way decoder and more than 6 ALUs. E.g. 6x ALU and 4x FP/ALU.

I emphasize that this is just my guess and nothing more.

 

[Wolverine2349]

Is it confirmed that Arrow Lake is going to max at 8 P cores and 16 e-cores?

Or any possibility of more P core variant like a 12 P core only die?

I have heard a possible refresh of 8 P and 32E.

Hopefully a 12 P core variant as well.

That way there is an option with 12 P cores on one tile/die and the best world class gaming CPU set and forget for all games of all types with no scheduling quirks of hybrid for the some games that have them (Even some modern devs cannot program for hybrid well) and with more games becoming a bit more threaded where more than 8 cores could help a little, 12 P core Arrow Lake would be a gamers dream for a set and forget it CPU solution with no Process Lasso and full WIN10 compatibility and full compatibility with 0- issues all games last 15-20 years and future games as well.

Please Intel release both. Or if not, the e-cores and thread director better be perfect to run any games last 15-20 years with no issues at all (full perfect performance as in as good as a 12 P core only model would do) with hybrid arch even games weirdly designed and no need to design with it in mind cause thread director is perfect for 0 issues with hybrid arch no more than a 12 P core non hybrid would run any better.

Though probably easier said than done on perfect thread director for 100% of games last 15-20 years for hybrid arch which is why 12 P core only variant would be nice. AMD not an answer as they have dual CCD/CCX and cross latency penalty and AMD design probably makes it much harder to make more than 8 cores per die unlike Intel's. Last CPU to have more than 8 cores of same type on single die was Comet Lake 10850K and 10900K. Come on Intel do it again with Arrow Lake.

 

[CouncilorIrissa]

Skymont is same area as Gracemont despite 2 node shrinks. So a lot more transistors.

Sounds fun. Will be even more fun if it outperforms (or equals) Golden Cope in INT.

 

[adroc_thurston]

That way there is an option with 12 P cores on one tile/die and the best world class gaming CPU

The thing has no chances against anything Zen5.

 

[dullard]

Or if not, the e-cores and thread director better be perfect to run any games last 15-20 years with no issues at all with hybrid arch even games weirdly designed and no need to design with it in mind cause thread director is perfect for 0 issues with hybrid arch no more than a 12 P core non hybrid would run any better.

You are basically arguing that the thread director is perfect with hyperthreading, you know where some threads are run at full speed and other threads at 10% to 30% of that speed. But, you are also arguing that the thread director is horrible with hybrid cores where some threads run at full speed and other threads run at 30% to 50% speed.

Now replace "thread director" with "game designer" in the paragraph above.

Really think about that and let it sink in.

 

[maddie]

You are basically arguing that the thread director is perfect with hyperthreading, you know where some threads are run at full speed and other threads at 10% to 30% of that speed. But, you are also arguing that the thread director is horrible with hybrid cores where some threads run at full speed and other threads run at 30% to 50% speed.

Now replace "thread director" with "game designer" in the paragraph above.

Really think about that and let it sink in.

Hyperthreading does not have full speed and (10% to 30% of that speed). It allows a 10% to 30% performance increase when using 2 threads, but the threads can just as easily be running at 65% & 65%.

 

[Wolverine2349]

You are basically arguing that the thread director is perfect with hyperthreading, you know where some threads are run at full speed and other threads at 10% to 30% of that speed. But, you are also arguing that the thread director is horrible with hybrid cores where some threads run at full speed and other threads run at 30% to 50% speed.

Now replace "thread director" with "game designer" in the paragraph above.

Really think about that and let it sink in.

No probably better without hyper threading. Just saying that it needs to be perfect or would be nice for a 12 P core variant. 12 P cores no HT would be great as well and best for games of all types past 10-15 years.

Problem is there are so many games already made and have and not patched up, so game designers cannot fix it. And even some of todays game designers do not code right for hybrid arch. But not much you can do to change that as some of those devs are out of business or purchased by others now. What can be done is multiple CPU options so all gaming scenarios easily covered which a 12 P core variant even with no HT on Lion Cove cores Arrow Lake CPU would do.

One thing that has been so great the last 20 years is the SMP compatibility of the Windows NT ecosystem on X86. Games of all types starting with native Windows 2000/XP based to present worked seamlessly as we went form single core HT to duals quads and beyond with massive IPC and clock speed increases and PCIe bus and storage advances and such. Have had that for over 20 years running with excelletn literally perfect compatibility due to CPUs. Would be nice to have CPUs choices with more cores that have that excellence of compatibility for best performance for todays and tomorrows games with just another 12 P core CPU die for sale as a choice.

Prior to Windows 2000 and XP it was a totally different era where OS architectures changed so much but in all far under 20 years. When excellent compatibility without big changes maintained for over 20 years with natives Windows NT (especially since Windows 7 then its more like 15 years) its almost taken for granted to keep up and stay like that. The hybrid arch has made that harder to much of an extent kind of like going form DOS based Windows to NT which was more than 20 years ago.

 

[Saylick]

A little more info is trickling out…