Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[DrMrLordX]

A good solution (and positive surprise) would be Intel reworking AVX to finally work more like SVE with the rumored introduction of AVX-1024, allowing E cores to handle all instruction even without native 1024 bit support.

That would be ideal. It would be difficult to maintain backwards compatibility with AVX/AVX2/AVX512 if they paid license fees to ARM/Fujitsu and adopted SVE2 (for reasons which were explained to me some time ago, but which I don't precisely remember; had something to do with the way register values were handled), but if they had their own version perhaps they could maintain that compatibility.

 

[nicalandia]

How do you know he's off base?

I am done with Raichu, I cant stand his Hentai Loving self. I open Twitter to find drawings of pubecent girls

 

[Hulk]

It's probably going to be TVB and single core only if I had to guess. Hitting 6ghz on more than one core is a lot to ask for. All core boost might go up by 100mhz or more, from 5.5ghz to 5.6/5.7ghz.



Perhaps. But out of the box power consumption and thermals is likely to be high no matter what without manual tuning. The auto voltages on these motherboards pump too much voltage into the CPU.

I would be impressed with an all-core 5.6GHz rating than a single or dual core 6GHz actually.

 

[Hulk]

I am done with Raichu, I cant stand his Hentai Loving self. I open Twitter to find drawings of pubecent girls

This is disturbingly all too true.

 

[eek2121]

Looks like MTL Desktop may be cancelled after all:

https://twitter.com/x/status/1606342626654896129

Arrow Lake SMID increased to 1024 bits from the looks of it:

https://twitter.com/x/status/1606344296126246918

Did Intel ever confirm a desktop MTL-S part? I don't recall seeing official materials about this. Please correct me if I'm wrong, because while I don't defend Intel about much, they are certainly much more open than AMD about future plans, to the point where the materials outrace my ability to embrace.

I've seen nothing to indicate that the roadmap shown a couple years ago hasn't changed much beyond acceleration of certain products.

 

[coercitiv]

Did Intel ever confirm a desktop MTL-S part? I don't recall seeing official materials about this.

AFAIK they never confirmed a desktop MTL part, so we might as well say the leak got cancelled instead

 

[uzzi38]

While I can appreciate the achievement of getting a production CPU to 6GHz if this is just a 2 core turbo 6GHz then it is useless outside of advertising. In reality there are no applications that benefit from 1 or 2 cores boosting ONLY when all other cores are not active. Without actually shutting down the other cores in the BIOS it's almost impossible to hit 5.8GHz on the 13900K I have found.

Now with that being said I would assume that if these super binned parts can hit 6GHz then perhaps they can do lower frequencies at lower voltage and power than the 13900K. We shall see.

Don't worry, it's not a 2 core turbo. It's a single binned core that only reaches those clocks under specific temperature limits.

 

[uzzi38]

I am done with Raichu, I cant stand his Hentai Loving self. I open Twitter to find drawings of pubecent girls

I've had him muted for over a year now for that very reason.

 

[uzzi38]

Did Intel ever confirm a desktop MTL-S part? I don't recall seeing official materials about this. Please correct me if I'm wrong, because while I don't defend Intel about much, they are certainly much more open than AMD about future plans, to the point where the materials outrace my ability to embrace.

The closest they did was they put out a slide saying Meteor Lake is designed to scale from 5W to 125W. The 125W would usually indicate a desktop SKU (same TDP as 12900K and 13900K afaik).

I've seen nothing to indicate that the roadmap shown a couple years ago hasn't changed much beyond acceleration of certain products.

A couple of years ago? No, things have DEFINITELY changed from that far back.

 

[Hulk]

Don't worry, it's not a 2 core turbo. It's a single binned core that only reaches those clocks under specific temperature limits.

As I wrote above hopefully these parts are at least higher quality than the standard 13900K's and can hit 5.5GHz all core at lower watts. Single core 6GHz is kind of silly if that's all you get for whatever astronomical price increase they will be charging.

I can just imagine how this conversation went when they started testing Raptors after production started.

"How are the parts clocking so far?"
"Pretty good, looks like we'll be able to offer 5.5GHz all core and 5.8GHz dual core turbo at the top of the stack with really good cooling."
"Great news."
"Oh yeah, we are finding some parts that will hit 6GHz on one core. For practical reasons it's useless but can we do anything with that?"
"Yes! Bin those separately. We'll stamp a nice big 6GHz on the box and add another couple hundred bucks to the price!"

 

[igor_kavinski]

AMD started this when they won the 1 GHz race with Athlon. Ever since Intel's been keen to reach the next GHz milestone first

 

[cebri1]

Did Intel ever confirm a desktop MTL-S part? I don't recall seeing official materials about this. Please correct me if I'm wrong, because while I don't defend Intel about much, they are certainly much more open than AMD about future plans, to the point where the materials outrace my ability to embrace.

I've seen nothing to indicate that the roadmap shown a couple years ago hasn't changed much beyond acceleration of certain products.

They adversited MTL to be a 5W to 125W cpu. I don't think a laptop chip on Intel 4 is going to get to 125W TDP.

 

[hemedans]

They adversited MTL to be a 5W to 125W cpu. I don't think a laptop chip on Intel 4 is going to get to 125W TDP.

i9 12900HK PL2 power consumption is 115W, and it can use up to 135W with short burst.

 

[scineram]

I am done with Raichu, I cant stand his Hentai Loving self. I open Twitter to find drawings of pubecent girls

Oh I see I must go and follow him.

 

[Geddagod]

i9 12900HK PL2 power consumption is 115W, and it can use up to 135W with short burst.

I believe they used the "base power" stat on the Intel ark specifications for the 5w to 125w CPU on the MTL slide. 125 watts is only relating to a desktop sku I believe. But who knows, maybe exist was right and the intel marketing team was just being shitty as usual haha
I'm hoping for a MTL-S sku, not because I really have a horse in the race, per se, but because I'm just really interested in Intel 4 power scaling and how much efficiency would be gained compared to the previous generations on Intel 7.

 

[mikk]

They also advertised MTL to have 192EUs in this slide which is false - 128EUs is the max option. I wouldn't read too much into his slide, even though MTL-S was definitely in the works or still is, we know from Intel non public sources, this is not the question. If it won't come they have cancelled it. It was clear from the beginning however that the mobile variants have priority and it makes sense. I wonder if we will hear something more from MTL mobile at CES.

 

[jpiniero]

I wonder if we will hear something more from MTL mobile at CES.

If you mean CES 2024, then maybe.

 

[Glo.]

They also advertised MTL to have 192EUs in this slide which is false - 128EUs is the max option. I wouldn't read too much into his slide, even though MTL-S was definitely in the works or still is, we know from Intel non public sources, this is not the question. If it won't come they have cancelled it. It was clear from the beginning however that the mobile variants have priority and it makes sense. I wonder if we will hear something more from MTL mobile at CES.

Who knows, maybe they found a way how to combine together GT2 and GT3 tiles and system will see them as one unit?



In all seriousness: if Intel would be able to do this, I would be genuinely amazed...

Edit: thinking about it more...

GT2 - 64 EUs, GT3 - 128 EUs. 64+128 = 192 EUs.

Adored leaked the Arrow Lake-P configuration and the tile having 320 EUs.

What if its the same thing, and GT2 - 64 EUs, and GT3 - 320 EUs. 64+320 = 384 EUs.

And best part:

The files also confirm the configurations of the upcoming integrated solutions. Intel is to double and then quadruple the GPU core count over Alder Lake iGPU solution.

• MTL_3x4x16= 192 (Execution Units)
• ARL_6x4x16= 384 (Execution Units)

Intel accidentally releases test driver for DG3 "Elasti" dGPU, Raptor/Meteor/Arrow/Lunar-Lake iGPUs - VideoCardz.com

Intel accidentally provides support for (yet) non-existing architectures A graphics test driver that was not supposed to be published on a public website is now available on the Intel website, as spotted by leaker KOMACHI. Intel NUC Kit 11th Gen driver 30.0.101.9999 a test driver with support...

videocardz.com

How possible this is?

 

[Exist50]

How do you know he's off base?

I have my reasons. Take that for whatever it's worth.

Supposing AVX1024 rumor is true, does this mean ARL will be P-cores only or they gonna beef up the E-cores with AVX1024 too? If the E-cores don't show up in ARL, it will confirm that hybrid cores was just a stopgap solution to have a fighting chance against AMD.

That's one obvious flaw with the rumor. And besides hybrid being beneficial regardless of other limits, with MTL/ARL limited to one compute tile, they would realistically struggle to match AMD's core counts with just P-cores.

I think it's obvious Intel wanted there to be a solution making P core with and E cores without AVX-512 at the same time possible, didn't manage to make it work in time and delayed the real solution. ARL may well be their second go at it.

I think it's far more likely they intend[ed] for Atom to support AVX-512 then try doubling the vector length again. Arguably 512 bits was already excessive.

A good solution (and positive surprise) would be Intel reworking AVX to finally work more like SVE with the rumored introduction of AVX-1024, allowing E cores to handle all instruction even without native 1024 bit support.

A vector width independent ISA would be nice, but I'm not sure how they'd do that without breaking some really core components of AVX itself. And to do that would be a very large scope.

 

[igor_kavinski]

A vector width independent ISA would be nice, but I'm not sure how they'd do that without breaking some really core components of AVX itself. And to do that would be a very large scope.

Their Israeli team loves challenges like that. They will create a new SIMD Director to handle the voodoo magic!

 

[moinmoin]

I think it's far more likely they intend[ed] for Atom to support AVX-512 then try doubling the vector length again. Arguably 512 bits was already excessive.

So you say Gracemont is a half baked incomplete silicon design originally intended to support AVX-512 frozen in time?

I personally find it to be far more likely that mixed ISA was intended from the beginning and a solution to make it work was intended to land in microcode, firmware and/or software/OS-support. The whole Intel Thread Director baggage and the fact Intel got Microsoft to launch a new Windows version in time imo all point to the latter. And it's here where work was incomplete so AVX-512 got retroactively disabled on P cores after the launch.

 

[Exist50]

So you say Gracemont is a half baked incomplete silicon design originally intended to support AVX-512 frozen in time?

I personally find it to be far more likely that mixed ISA was intended from the beginning and a solution to make it work was intended to land in microcode, firmware and/or software/OS-support. The whole Intel Thread Director baggage and the fact Intel got Microsoft to launch a new Windows version in time imo all point to the latter. And it's here where work was incomplete so AVX-512 got retroactively disabled on P cores after the launch.

No, I doubt Gracemont was ever intended to support more than AVX2. The jump from SSE to AVX2 is large enough by itself. But maybe they thought they'd add AVX-512 for Skymont and it wasn't a big deal to skip it for a gen. I really doubt a software/OS solution was ever in the cards though. Would be a mess all around. They disabled AVX-512 after launch probably because someone pointed out that would be a feature regression going from the lower end to the higher end chips.

Edit: Typo. Meant AVX2 for Gracemont.

 

[moinmoin]

I really doubt a software/OS solution was ever in the cards though. Would be a mess all around. They disabled AVX-512 after launch probably because someone pointed out that would be a feature regression going from the lower end to the higher end chips.

But that doesn't make sense in several ways. Why waste the area necessary for AVX-512 support if software/OS solution was never in the cards, and continue wasting it after it's even disabled and fused off as an optional feature?

 

[igor_kavinski]

Maybe Intel had a solution but it required support from Microsoft and Microsoft refused to implement it because doing so would increase their OS scheduler complexity too much. In the end, Intel decided that AVX-512 wasn't worth the hassle on the client side anymore. The Microsoft refusal would make sense if this support was going to be there for only a few generations of Intel CPUs and then Intel was going to move on to AVX1024 anyway. Microsoft simply said, No thanks!

 

[scineram]

Without this bug.<redacted> thing OS support is not even relevant. Userspace programs can just query cpuid and run their own codepaths as they want on any normal processor.

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