Well my entire tirade started precisely because some people don't like to double-check what they post. And apparently, such incidents are simply glossed over or pushed under the carpet in this so-called Intel thread. Just look at my previous post just above yours.Posting false information is against the forum rules and should be reported for moderation using the report button. This is an Intel topic, can you at least try to keep it to Intel?
Do you have *actual* examples of AVX-512 giving the purported uplifts over 256b and 128b versions? Or did Intel invent it only to calculate digits of irrational numbers?
Epyc 'destroys' Skylake-SP in STREAM Triad. I wonder why.
Exceed L1D with large data sets in real-world code and AVX2 lead vanishes into thin air. So much for being 3X faster.
Posting false information is against the forum rules and should be reported for moderation using the report button. This is an Intel topic, can you at least try to keep it to Intel?
Do you not understand why that happens, or just pretending not to?It turns out in applications more real world than STREAM Triad, advantage of AVX2 and AVX512 does not vanish ( not to mention that in original claim article, 8 core ryzen with 8xL1/L2 BW resources is being compared to 4 cores of Skylake and achieves only 1.6x score).
Oh, you haven't heard about high frequency microarchitecture designs? Go compare Bulldozer to it's predecessor, Thuban, (clock for clock) and you'll understand why Bulldozer failed. Hint: low clocks.
IPC = Instructions per clock, meaning you take frequency out of the equation and only focus on what remains - the architecture. Thuban was faster than Bulldozer precisely because Bulldozer had lower IPC due to it's weaker cores, CMT and shared FPU.Oh, you haven't heard about high frequency microarchitecture designs? Go compare Bulldozer to it's predecessor, Thuban, (clock for clock) and you'll understand why Bulldozer failed. Hint: low clocks.
You think Sandy Bridge, and now Kabylake, being able to hit 5ghz for daily operation is by accident, right? It has nothing to do with design, right?
Haha! You still don't get it. Hint: Clocks, clocks, clocks!!! The 'I' and 'P' mean nothing without the 'C' (cycles.) So, no, you don't take frequency out of the equation, ever!IPC = Instructions per clock, meaning you take frequency out of the equation and only focus on what remains - the architecture. Thuban was faster than Bulldozer precisely because Bulldozer had lower IPC due to it's weaker cores, CMT and shared FPU.
Large data set? Real-world code? Try Ansys Fluent. http://www.ansys.com/products/fluids It is used by just about any major manufacturer/designer for airplanes, car aerodynamics, chemical reactions, heat transfer (such as cooling fans in computers), oil pumping, etc.Exceed L1D with large data sets in real-world code and AVX2 lead vanishes into thin air.
Ansys Fluent is software that can get say 99.46% scaling efficiency with 144 cores as an example:In Fluent, we’ve added support for Intel® Advanced Vector Extensions 2 (AVX2) optimized binary...Our benchmark results also show the Intel Xeon Gold 6148 processor boosts performance for ANSYS Fluent 18.1 by up to 41% versus a previous-generation processor — and provides up to 34% higher performance per core.
Even mods here are pro-AMD propaganda. It's a shame Anandtech's reviews don't fit into their narratives. A 7800x beating 1800x on this site's review is too hard to swallow.On second thought, nevermind, I'm not a Mod.
On 28nm the best it could do was 5GHz but at an eye watering TDP. In spite of that we all admit that it was a bad CPU architecture to begin with, and will always have lower IPC.Haha! You still don't get it. Hint: Clocks, clocks, clocks!!! The 'I' and 'P' mean nothing without the 'C' (cycles.) So, no, you don't take frequency out of the equation, ever!
Bulldozer, was a high frequency design. It was supposed to be a speed demon and would've made up for it's relatively weak "ipc" had it managed to run at intended clocks. So, knowing very well the trade-off here, it'll be disingenuous to do a clock for clock comparison between Bulldozer and Thuban.....
This is the last time I'm going to debate you on this due to off-topic. Sorry guys.
You can choose to go with whatever facts you like, but you can't get over the fact that you provided outright false information(basically lied) regarding y-cruncher. If you remove outliers like y-cruncher there are no gains to be made from AVX512, and hence your 15 percent IPC advantage comes down to 10% or less.So somehow we went from guy who was excluding a bunch of benchmarks that did not fit his narrative that Ryzen has Skylake IPC, into looking at realworldliness of benchmarks and stress tools? This discussion is over for me, basic facts do not change, Skylake has >15% IPC advantage and up to 25% clock advantage when overclocked. No goal shifting and fact twisting can change those facts.
One can always find "reasons" why some tests are synthetic, or "biased" or not "real world" enough, but if you remove true outliers like Cinebench or y-Cruncher, IPC advantage is still Intel's. "benchmark suites" like GB4 or simple tools like latest CPU-Z confirm substantial advantage in ST for Skylake.
Large data set? Real-world code? Try Ansys Fluent. http://www.ansys.com/products/fluids It is used by just about any major manufacturer/designer for airplanes, car aerodynamics, chemical reactions, heat transfer (such as cooling fans in computers), oil pumping, etc.
What happens with AVX2 in probably the most common industrial use for number crunching of large data sets? http://www.ansys-blog.com/boost-ansys-performance-intel-technologies/
Ansys Fluent is software that can get say 99.46% scaling efficiency with 144 cores as an example:
http://www.ansys.com/Solutions/Solu...marks-release-17/flow-through-a-combustor-12m
Running with hundreds/thousands of cores is fairly common. This isn't calculating pi. This is multi-million dollar simulations. AVX-512 data isn't out yet. But Ansys updates their software (and thus benchmarks) around October of most years, so maybe it will be available then.
Please share with us the AVX2, AVX-512 benchmarks of their code. More data is always better.In discussion with people who write their own Lattice QCD and MHD/Plasma Physics codes, I know very well when it's about memory bottlenecks and when it isn't.
Interesting that just today, while quoting you, I posted this about processors in between:Interesting that your arguments always revolve around Pentium G4560s and cheap OEM builds on one end and hundreds of thousands of cores running weeks of simulations on the other with little in between.
A little information about myself: I'm a cheapskate personally and professionally I ran ANSYS Fluent and coded my own mathematical simulation software for years (I'm no longer in that line of work though and do not have personal AVX-512 experience). So, yes, I do talk about both ends of the spectrum. But I'm certainly not limited to those extremes.I think the 1600X chip is the best up-front value of all chips at the moment. The 1600X has faster speed and 2 more cores than the 1500X, for only $40 more. But if you take total cost of ownership into account, the lower power 1600 is probably the best buy. To keep to the topic of the thread though, the upcoming Intel 8600 might win that best buy award from me if the rumored speeds are true
Here: certain QCD kernels on Knight's Landing are only 20% faster using AVX512 over AVX2.Please share with us the AVX2, AVX-512 benchmarks of their code. More data is always better.
How about using explicit vectorization instead of compiler autovectorization for ease of use, avoiding verbose compiler-generated code, but with similar levels of performance uplift across a number of different use cases?CMSSW (Reco and HLT)
–Standard build (-O2, -ftree-vectorize, SSE3)
» HSW up to 25% faster than SB for selected modules
» In average 15-20% faster than SB
–Native build (-O2, -ftree-vectorize, -march=haswell)
»Between 2% and 4% slower than Standard build
Here: certain QCD kernels on Knight's Landing are only 20% faster using AVX512 over AVX2.
http://www.nersc.gov/users/computat...ce/application-case-studies/qphix-case-study/
How about something from CMS@Cern:
Includes benchmarks that fit into the cache - Scimark, actual library function to evaluate multivariate PDFs that are heavily dependent on memory bandwidth, and finally includes the CMSSW software framework, the results of the latter showing performance regression:
How about using explicit vectorization instead of compiler autovectorization for ease of use, avoiding verbose compiler-generated code, but with similar levels of performance uplift across a number of different use cases?
https://github.com/VcDevel/Vc
By comparison, your Ansys link was basically a marketing slide.
I'm not talking about the data center, and neither do I care. HPC is mostly what I look at.Major data center customers want Skylake-SP so badly that ~30 cos collectively bought 500K pre-PRQ parts. I strongly suspect that the AVX-512 performance that you keep bashing ad nauseum was a significant part of the value prop.
You really need to let it go, dude.
https://videocardz.com/71269/intel-core-x-series-full-specs-revealed
Full Spec list for Skylake-X. The 18 core has a base clock of 2.6 with TB3 of 4.4 while having a TDP of 165.
Really? Where does Apple compete with Intel, and what does Intel need to do remain competitive with them?
Apple has already shown that they can beat Core's performance at the same power levels. It's only a matter of time.
OR they move Macs to an Ax SoC, it's not like they haven;t done this before.Until what? Apple starts selling CPUs to third parties? iPads replace everyone's laptops? iPads weren't doing so well the last time I checked.
OR they move Macs to an Ax SoC, it's not like they haven;t done this before.
So, in defense of your statement that AVX2 leads "vanish into thin air" you post links that show:...
By comparison, your Ansys link was basically a marketing slide.