Intel vs. IBM fab process

[Gunnar]

These two companies have huge budgets in R&D for fabricating semi-conductors, so I was wondering who uses a more advanced process for fabricating their chips?

As I understand it, Intel was first to the 90nm process, that in itself is quite an accomplishment. In addition, Intel is a leader in packaging, coming up with new and alternative package designs and configurations (FCPGA, organic package, BGA, etc.). IBM seems to have a more advanced materials team though, leveraging SOI.

I never took an advanced VLSI class so I don't know for sure, but I think that the SOI gates have a longer switch time (remembering some slide for extra credit a couple years ago). And the only real advantage to SOI is the ability to produce copper chips.

Anyone here a VLSI EE?

 

[Falloutboy]

both are ahving issues with 90nm but I think IBM is getting them worked out. not sure about intel thier pretty hush hush about thier "issues". right now though I'd go with IBM, microsoft wouldn't of picked them otherwise for the xbox2

 

[OddTSi]

Microsoft picked them for the XBox2 because they were the cheapest fab capable of handling the type of output that they need. Microsoft has stated that they don't want to lose as much money per console as they do/did with the XBox. Hence the reason they went with SiS, and ATi. Lowest bidder (that's still capable of delivering what they need) gets it.

 

[biostud]

It will be interesting to see how much the AT forums knows about the actual process of making the chip.

Personally I doubt that many knows what actually happens in the factories. Could be some kind of dark ritual that made it all work

 

[Sideswipe001]

You mean, they aren't put together by Voodoo Black Magic?

 

[beer]

Originally posted by: biostud666
It will be interesting to see how much the AT forums knows about the actual process of making the chip.

Personally I doubt that many knows what actually happens in the factories. Could be some kind of dark ritual that made it all work

I agree. Next semester I have a microelectronic fabrication techniques course. I'll get back to ya in a few months

 

[pm]

"Better" is a nice subjective statement and even "advanced" is a bit subjective too.

May I suggest "High Performance CMOS Device on SOI for 90nm Technology Enhanced by RSD (Raised Source/Drain) and Thermal Cycle Spacer Engineering" by H. Park, et.al. Proceedings of theIEDM 2003 Conference for the IBM paper. And "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors" by T. Ghani, et.al. Proceedings of the IEDM 2003 Conference for the Intel paper. If you look at these two, you can compare and contrast - at least at the transistor level.

In summary, IBM's process is a 90nm process with a 40nm effective gate length. Transitors drive 420uA/um PMOS and 820 uA/um NMOS at 1V VDD with an IOff current of 40nA/um. Intel's process is a 90nm process with a mixed45nm effective gate length (NMOS) and 50nm (PMOS). Transistors drive 700uA/um PMOS and 1260uA/um NMOS at 1.2V VDD with an IOff current of 40nA/u m. IBM is using an interesting RSD technique to improve series resistance of the contacts and to improve short channel effects and they have some interesting data on thermal cycling improvements. Intel spends much of it's paper taking about the strained silicon method and the gains in current drive strength from it and spend a bit talking about the manufacturability of the the technique.

But even with raw numbers, it's pretty subjective which is better anyway. Is better lower power? Faster FETs? Higher Yield? If it's all of the above, how do you wiegh each of these against the other - since lower power and faster FETs are usually opposed and faster FETs and higher yield are opposed as well? Then there's the problem that different companies measure at different operating points and use different transistor performance benchmarks - although this problem has gotten better in recent years with a lot less use of the controversial Tf measurement. So once you decide what you think is important, it's hard to compare oranges with oranges since one 'orange' is at 1.2V and the other is at 1V.

I'll leave you to decide who has the better process... I know which one I think is better.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.

 

[beer]

Originally posted by: pm
"Better" is a nice subjective statement and even "advanced" is a bit subjective too.

May I suggest "High Performance CMOS Device on SOI for 90nm Technology Enhanced by RSD (Raised Source/Drain) and Thermal Cycle Spacer Engineering" by H. Park, et.al. Proceedings of theIEDM 2003 Conference for the IBM paper. And "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors" by T. Ghani, et.al. Proceedings of the IEDM 2003 Conference for the Intel paper. If you look at these two, you can compare and contrast - at least at the transistor level.

In summary, IBM's process is a 90nm process with a 40nm effective gate length. Transitors drive 420uA/um PMOS and 820 uA/um NMOS at 1V VDD with an IOff current of 40nA/um. Intel's process is a 90nm process with a mixed45nm effective gate length (NMOS) and 50nm (PMOS). Transistors drive 700uA/um PMOS and 1260uA/um NMOS at 1.2V VDD with an IOff current of 40nA/u m. IBM is using an interesting RSD technique to improve series resistance of the contacts and to improve short channel effects and they have some interesting data on thermal cycling improvements. Intel spends much of it's paper taking about the strained silicon method and the gains in current drive strength from it and spend a bit talking about the manufacturability of the the technique.

But even with raw numbers, it's pretty subjective which is better anyway. Is better lower power? Faster FETs? Higher Yield? If it's all of the above, how do you wiegh each of these against the other - since lower power and faster FETs are usually opposed and faster FETs and higher yield are opposed as well? Then there's the problem that different companies measure at different operating points and use different transistor performance benchmarks - although this problem has gotten better in recent years with a lot less use of the controversial Tf measurement. So once you decide what you think is important, it's hard to compare oranges with oranges since one 'orange' is at 1.2V and the other is at 1V.

I'll leave you to decide who has the better process... I know which one I think is better.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.

Your ideas are intriguing and I wish to subscribe to your newsletter.

 

[pm]

Beer, I don't what you are talking about. What newsletter?


I remembered after I posted that the real 90nm papers were from 2002, not 2003. So, Intels was " A 90nm Logic Technology Featuring Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD and 1um^2 SRAM Cell" by S. Thompson, et.al. IEDM 2002. And IBM's was " A High Performance 90nm SOI Technology with 0.992 um^2 6T-SRAM Cell" by M. Khare, et.al, IEDM 2002.

The data is similar to the above but it elaborates on SRAM sizes, and talks about interconnects as well. These two are probably the better papers to look at since process technology is more than just FETs. Some other companies presented back then too so you can look at TSMC's data (310/670 uA/um PMOS/NMOS with 10nA/um Ioff) among other companies as well.

 

[Wingznut]

Originally posted by: biostud666
It will be interesting to see how much the AT forums knows about the actual process of making the chip.

You might be surprised as to how many very knowledgeable people hang out around here.

Originally posted by: Gunnar
And the only real advantage to SOI is the ability to produce copper chips.

Using Cu metal layers and using SOI wafers are very different animals. One is not dependant on the other at all.

Originally posted by: Falloutboy525
both are ahving issues with 90nm but I think IBM is getting them worked out. not sure about intel thier pretty hush hush about thier "issues". right now though I'd go with IBM, microsoft wouldn't of picked them otherwise for the xbox2

Drawing the conclusion that one fab is better than another, because MS chose them for the Xbox 2, is hardly an accurate conclusion. Nobody seems to take into the account that maybe, just maybe, AMD and Intel didn't get the contract, because they didn't really want the contract. Not to mention that the Xbox 2 cpu will most likely be built on a .065µ process.

 

[beer]

Originally posted by: pm
Beer, I don't what you are talking about. What newsletter?


I remembered after I posted that the real 90nm papers were from 2002, not 2003. So, Intels was " A 90nm Logic Technology Featuring Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD and 1um^2 SRAM Cell" by S. Thompson, et.al. IEDM 2002. And IBM's was " A High Performance 90nm SOI Technology with 0.992 um^2 6T-SRAM Cell" by M. Khare, et.al, IEDM 2002.

The data is similar to the above but it elaborates on SRAM sizes, and talks about interconnects as well. These two are probably the better papers to look at since process technology is more than just FETs. Some other companies presented back then too so you can look at TSMC's data (310/670 uA/um PMOS/NMOS with 10nA/um Ioff) among other companies as well.

It's a quote from the simpsons. If I recall, Lisa goes all intellectual and way over Homer's head, and Homer looks blindly and says "hmm, I find your ideas intriguing and wish to subscribe to your newsletter." Everything in life can be described in terms of Simpsons

 

[Gunnar]

Wow, I guess there is a lot more to process technology than just shrinking gate widths and decreasing switching time.

As some who is far removed from layout, this is all new to me. How important is process technology to the architecture people? Do the engineers doing the VHDL care about process? Or is a microprocessor architected independent of process?

 

[CTho9305]

Gunnar, SOI is supposed to reduce leakage. Apparently it can cause thermal problems too, though, since the insulator used doesn't conduct heat very well.

pm You don't have numbers for Intel's process at 1V? (I have IBM info at 1.2V... but I don't know what's NDA and what isn't, so I'll leave it to you ).

 

[pm]

Originally posted by: CTho9305
Gunnar, SOI is supposed to reduce leakage. Apparently it can cause thermal problems too, though, since the insulator used doesn't conduct heat very well.

SOI reduces power by lowering parastic diffusion cap, and reducing body leakage. It has a slight decrease in M1 cap. It slightly improves performance due to the reduced cap. It eliminates a fairly rare problem called "latch-up" and it slightly improves SRAM density. For those benefits, the negatives are that it increases wafer cost, can reduce yield (not in theory, but it has done in practice), heat transfer is reduced by the insulator, and you have some interesting design challenges regarding the hysteresis effect (which in the hands of an aggressive designer can be a pro but is nearly always a con).

pm You don't have numbers for Intel's process at 1V? (I have IBM info at 1.2V... but I don't know what's NDA and what isn't, so I'll leave it to you ).

IBM's 1.2V numbers? Low Vt or high? With self-heating or without?

They weren't in the 2003 paper, but they are in a table in the 2002 paper. At 1.2V, with no self-heating using high-Vt FETs, PMOS: 599uA/um NMOS: 1322uA/um and 70nA/um Ioff.

 

[jagec]

Originally posted by: biostud666
It will be interesting to see how much the AT forums knows about the actual process of making the chip.

Personally I doubt that many knows what actually happens in the factories. Could be some kind of dark ritual that made it all work

I have a general idea, but I've never actually seen the machines.

I was going to get an internship at Intel this summer but I never heard back from them

 

[Zebo]

Moore "law" is dead due to transistors only being 5-10 atoms thick right now, and you can't defeat the law of physics/chemistry/materials science to make them any smaller for normal speed bumbs as in the past. I think AMD is more "advanced" or "on top of things" if you will simply because they have more horsies/hz in their chips, run cooler and less leakage right now. This could all change when the make the 90nm bump to but after that, if succesful I think it's done.

 

[pm]

Originally posted by: Gunnar
As some who is far removed from layout, this is all new to me. How important is process technology to the architecture people? Do the engineers doing the VHDL care about process? Or is a microprocessor architected independent of process?

Interesting questions, Gunnar. I define the architecture to be the instruction set, the number of registers, the assembly code, etc. Basically all of the stuff in IA32 that has been fundamentally the same since the i386. From that standpoint, the architecture of a chip is completely independent of process technology.

The actual implementation of this ISA (Instruction Set Architecture) into a chip such as the Pentium 4 is what is called the microachitecture. The implementation of an architecture into a chip. Definitely a microprocessor is not microarchitected independent of process. But at the same time, I can watch the eyes of our architects glaze over when I start talking about saturation current and low threshold voltage transistors. In order to hit power and frequency goals, a design has to have some idea of how fast FETs are, how fast the interconnect is, and how much leakage there is. If you leave these out of your design considerations or you don't represent them accurately, then you aren't likely to have a design that completes to targeted goals on schedule. So they are modelled fairly loosely into the model one way or another. The architects don't need to know about the details, but they are aware of the process.

 

[beer]

Originally posted by: Zebo
Moore "law" is dead due to transistors only being 5-10 atoms thick right now, and you can't defeat the law of physics/chemistry/materials science to make them any smaller for normal speed bumbs as in the past. I think AMD is more "advanced" or "on top of things" if you will simply because they have more horsies/hz in their chips, run cooler and less leakage right now. This could all change when the make the 90nm bump to but after that, if succesful I think it's done.

I really think you're minimalizing the technical nature of the process far, FAR too much. I've only had one VHDL course and one solid state electronics course, and while all of PM's stuff is way over my head, I think you are leaving out too many variables to make your assertion. I honestly can say that I think you have no clue what you are talking about, and haven't read anything more than general-interest, non-engineer targeted magazines. Or so it appears to me.

 

[DAPUNISHER]

Bump for one of the best threads in a good while. pm posted so you know it's good! :beer:

 

[Zebo]

Originally posted by: beer

Originally posted by: Zebo
Moore "law" is dead due to transistors only being 5-10 atoms thick right now, and you can't defeat the law of physics/chemistry/materials science to make them any smaller for normal speed bumbs as in the past. I think AMD is more "advanced" or "on top of things" if you will simply because they have more horsies/hz in their chips, run cooler and less leakage right now. This could all change when the make the 90nm bump to but after that, if succesful I think it's done.

I really think you're minimalizing the technical nature of the process far, FAR too much. I've only had one VHDL course and one solid state electronics course, and while all of PM's stuff is way over my head, I think you are leaving out too many variables to make your assertion. I honestly can say that I think you have no clue what you are talking about, and haven't read anything more than general-interest, non-engineer targeted magazines. Or so it appears to me.

"The real roadmaps going forward are going to be innovation roadmaps, not lithography roadmaps. It's not just lithography that is driving progress

EE Times "engineering targeted" enough for ya?

 

[beer]

There's nothing in the article more complex than mentioning cmos and BJTs...

 

[n0cmonkey]

Do we need to turn this into a flame war? I was highly enjoying the glaze over my eyes while reading the posts from the Intel guys, and you two have to kill my buzz.

 

[CTho9305]

Originally posted by: pm
IBM's 1.2V numbers? Low Vt or high? With self-heating or without?

I was on my way to work, and realized I needed to make it a more specific question right after posting .

I get the impression that architects don't need to know much more detail than "you can get about x gates in a cycle", so that they come up with stuff that can be implemented.

 

[Wingznut]

Originally posted by: Zebo
Moore "law" is dead due to transistors only being 5-10 atoms thick right now, and you can't defeat the law of physics/chemistry/materials science to make them any smaller for normal speed bumbs as in the past.

I believe what you are referring to is the thickness of the gate oxides (gate insulators). And you are right... Insulating the gates from leakage and capacitance is definitely a challenge.

But imagine if there are advances in the types of gate insulation materials (i.e. high-k dielectric)... Or the ability to use a better conductor at the gate (i.e. Cu or Ni). Dual and tri-gate transistors are also very intriguing.
Not that those things don't bring about their own set of challenges.

 

[pm]

Originally posted by: Zebo
Moore "law" is dead due to transistors only being 5-10 atoms thick right now, and you can't defeat the law of physics/chemistry/materials science to make them any smaller for normal speed bumbs as in the past.

"Moore's Law" is dead? I remember reading that sometime in the early 80's too. I wouldn't advise going to Vegas and putting any money down on that assertion. Industries that are worth hundreds of billions of dollars don't just die suddenly. Beyond the fact that it's not the thickness of the gate that makes Moore's Law a reality (ie. we could stop shrinking the gate thickness altogether and continue to make progress), there are plenty of alternative materials and topologies that could be used. Conventional CMOS will most likely take us down to the 16nm node... maybe lower.

May I recommend the ITRS (International Technology Roadmap for Semiconductors) 2003 Edition for a little light reading on the subject along with a detailed roadmap of how the semiconductor industry is planning to continue advancing "Moore's Law".

The article you posted is interesting. I personally don't agree with several assertions in there, although I can see where the author is coming from. Scaling certainly is not dead - although there are increasing challenges. The lithographic definition of process technology is definitely not meaningless, although I would agree that south of 0.25um it started to lose some of it's meaning. Scalings challenges have little to do with increasing gate leakage... I see Ioff as being a bigger problem in the short term. My take on the article in the link is that it's a technologist attempting to be provacative in the hopes of generating discussion.

I think AMD is more "advanced" or "on top of things" if you will simply because they have more horsies/hz in their chips, run cooler and less leakage right now. This could all change when the make the 90nm bump to but after that, if succesful I think it's done.

These are primarily microarchitectural implementation issues and are outside the scope of this thread. As far as CPI and low power microprocessors, you might want to look at the Intel XScale PXA27x series and the Intel Pentium M microprocessors.

As far as less leakage, I'm not aware of a paper from AMD on their process technology (if anyone can point me to one, I'd be grateful), although I could make a educated guess that their numbers most likely bear a strong similarity to IBM's due to the collaboration between the two companies on 90nm.