Info LPDDR6 @ Q3-2024: Mother of All CPU Upgrades

[Tuna-Fish]

I do wonder what that means for consumer zen6 and DDR5 support.

I think there will not be Zen6 with LPDDR6 for desktop. Tigerick is a bit overly optimistic about timeline in this thread, with the spec only coming this year, if Zen6 releases next year the memory won't be ready for it. Maybe an APU with LPDDR6 support near the end of the Zen6 era.

Are they really gonna support 192bit LPDDR6 and 128bit DDR5 from the same controller? If not it's EOL for AM5.

This is the AMD way, EOL for AM5 when AM6 launches, with no support for the past memory standard for new chips.

But this is still ways off, AM5 only got to market more than 2 years after the DDR5 standard was published, and the DDR5 standard was delayed for two years. LPDDR6 is coming on time.

I think the first date for early LPDDR6 systems is very late 2026 or early 2027, with mass market adoption only later in 2027.

 

[Doug S]

24 bit channels? What the heck? I'd love to hear the logic on why you go from 16 to 24 instead of 32. That will require three chips to make a minimum sized LPDDR6 package now. Given that 16 Gb DRAMs are going out of production I guess 9 GB (and soon after that 12 GB) becomes the smallest possible unit for LPDDR6 unless someone makes an x24 DRAM.

Not being a power of 2 seems like a pain for filling cache lines, but I assume it works out one way or another or this wouldn't have been anointed the standard. Love to be a fly on the wall during the early standards meetings when someone pipes up with "how about we go to 24 bit channels" and see what was said lol

 

[Glo.]

24 bit channels? What the heck? I'd love to hear the logic on why you go from 16 to 24 instead of 32. That will require three chips to make a minimum sized LPDDR6 package now. Given that 16 Gb DRAMs are going out of production I guess 9 GB (and soon after that 12 GB) becomes the smallest possible unit for LPDDR6 unless someone makes an x24 DRAM.

Not being a power of 2 seems like a pain for filling cache lines, but I assume it works out one way or another or this wouldn't have been anointed the standard. Love to be a fly on the wall during the early standards meetings when someone pipes up with "how about we go to 24 bit channels" and see what was said lol

If its for LPCAMM - 192 bit is created from 8*24 bit channels and 384 - 16*24 bit channels. So it does in the end make sense.

 

[Tuna-Fish]

I'd love to hear the logic on why you go from 16 to 24 instead of 32. That will require three chips to make a minimum sized LPDDR6 package now. Given that 16 Gb DRAMs are going out of production I guess 9 GB (and soon after that 12 GB) becomes the smallest possible unit for LPDDR6 unless someone makes an x24 DRAM.

Not being a power of 2 seems like a pain for filling cache lines, but I assume it works out one way or another or this wouldn't have been anointed the standard. Love to be a fly on the wall during the early standards meetings when someone pipes up with "how about we go to 24 bit channels" and see what was said lol

None of this is true, I recommend reading the posts.

The channel width is 24 (2*12-wide subchannel), the burst length is also 24, meaning that a single transfer is 576 bits (288), consisting of 512 bits of data and 64 bits of metadata, of which half is defined to be always available to the host as it sees fit (which is absolutely amazing, it will allow ECC on every device, ECC over 32 bytes needs 12 bits, leaving 4, which is the amount of bits needed for CHERI), and the other half is either used for power saving through data bit inversion or a separate link protection scheme.

 

[Doug S]

None of this is true, I recommend reading the posts.

The channel width is 24 (2*12-wide subchannel), the burst length is also 24, meaning that a single transfer is 576 bits (288), consisting of 512 bits of data and 64 bits of metadata, of which half is defined to be always available to the host as it sees fit (which is absolutely amazing, it will allow ECC on every device, ECC over 32 bytes needs 12 bits, leaving 4, which is the amount of bits needed for CHERI), and the other half is either used for power saving through data bit inversion or a separate link protection scheme.

Reading what posts?

If this means we'll get built in ECC I'm all for it, and a lot more enthusiastic about LPDDR6 than I have been!

 

[Tuna-Fish]

Reading what posts?

If this means we'll get built in ECC I'm all for it, and a lot more enthusiastic about LPDDR6 than I have been!

Darkmont on twitter posted some slides from recent JEDEC symposium, here's a direct link to the X thread:

https://twitter.com/x/status/1792839851618017349

 

[FlameTail]

Darkmont on twitter posted some slides from recent JEDEC symposium, here's a direct link to the X thread:

https://twitter.com/x/status/1792839851618017349

Isn't that 24-bit width going to be problematic?

That means no more 8 GB, 16 GB, 32 GB,... capacities.

 

[Doug S]

Found the full slide deck online (maybe it was posted in that Twitter thread but I don't have an account and can't see replies)

https://www.jedec.org/sites/default/files/Brett Murdock_FINAL_Mobile_2024.pdf

Interesting stuff about the extra bits, though I am less optimistic about ECC being supported since I could easily see the user defined half being used for some type of tagging rather than ECC, and the built-in half being used for lower power rather than link protection.

I do find it funny that slide 10 echoes my initial take: "12 Data pins? That’s not very power-of-two-ish…"

I guess they were tired of hearing that every time they told someone the new standard was 24 bit channels!

 

[adroc_thurston]

Isn't that 24-bit width going to be problematic?

no.

 

[Doug S]

Isn't that 24-bit width going to be problematic?

That means no more 8 GB, 16 GB, 32 GB,... capacities.

They can still make arrays with that "actual" size, but they'll actually have 12.5% more bits due to the extra 32 bits for every 256. I saw claims elsewhere that they'll be making x12 and x24 DRAMs, I guess we'll see. But would it be a terrible thing if we ended up with 12 GB or 18 GB or 23 GB type capacities? While it matters at low levels there's no reason to care about power of 2 for total RAM capacity, and that's not enforced in any way now.

Heck my mom's PC has 10 GB, because it was originally purchased with 2 GB but I added 8 more as a mid life kicker along with an SSD. Works just fine despite not being power of 2.

 

[FlameTail]

I guess they were tired of hearing that every time they told someone the new standard was 24 bit channels!

What are the implications of this?

Does it mean LPDDR6 SoCs are incapable of having 64-bit/128-bit/256 bit capacities?

I wonder if mainstream SoCs will then downgrade from 128 bit to 96 bit, or upgrade from 128 bit to 196 bit?

The latter would be great. Here's a reddit post advocating for wider bus widths in SoCs/APUs:

https://www.reddit.com/r/hardware/comments/1cg16ah/opinion_its_about_time_that_mainstream_laptop

 

[FlameTail]

They can still make arrays with that "actual" size, but they'll actually have 12.5% more bits due to the extra 32 bits for every 256. I saw claims elsewhere that they'll be making x12 and x24 DRAMs, I guess we'll see. But would it be a terrible thing if we ended up with 12 GB or 18 GB or 24 GB type capacities? While it matters at low levels there's no reason to care about power of 2 for total RAM capacity, and that's not enforced in any way.

It would break some industry standards.

For instance, Microsoft recently mandated that all Copilot+ PCs should have a minimum of 16 GB RAM. So if LPDDR6 is going to switch away from power of 2, then Microsoft might have to reduce the requirement to 12 GB or increase it to 24 GB?

 

[Doug S]

It would break some industry standards.

For instance, Microsoft recently mandated that all Copilot+ PCs should have a minimum of 16 GB RAM. So if LPDDR6 is going to switch away from power of 2, then Microsoft might have to reduce the requirement to 12 GB or increase it to 24 GB?

How does that break the standard? If they say 16 they mean 16. 12 GB was already a possibility using 24 Gb DRAMs and they didn't say 12 so they won't reduce it because of LPDDR6.

And I'm sure Microsoft was not caught unaware by LPDDR6, they likely had someone involved with that since they do built their own hardware and would want to know what's coming down the pike.

 

[FlameTail]

How does that break the standard? If they say 16 they mean 16. 12 GB was already a possibility using 24 Gb DRAMs and they didn't say 12 so they won't reduce it because of LPDDR6.

And I'm sure Microsoft was not caught unaware by LPDDR6, they likely had someone involved with that since they do built their own hardware and would want to know what's coming down the pike.

Yeah but I was wondering what happens to all the laptops with 16 GB LPDDR5X, once they upgrade to LPDDR6?

So they bump up to 24 GB?

Edit: 18 GB it is! I forgot that18 GB is possible by using 3x 6 GB chips.

With LPDDR5, the pattern was 8, 12, 16, 24, 32, 48, 64 etc..

With LPDDR6, it will be 12, 18, 24, 36, 48, 72, 96, 144, 192 etc..

Sounds very oddball, but guess we'll get used to it.

 

[igor_kavinski]

Edit: 18 GB it is! I forgot that18 GB is possible by using 3x 6 GB chips.

Aren't there better things to wonder about?

Welcome back! How was the coma? Did you visit any strange worlds?

 

[FlameTail]

Aren't there better things to wonder about?

Certainly

Welcome back!

Thank you.

So if LPDDR6 will make 192 bit buses standard for mainstream SoCs, I am all in for it. When are we expecting devices with LPDDR6?

 

[igor_kavinski]

When are we expecting devices with LPDDR6?

Samsung keen to start making LPDDR6 RAM ahead of Snapdragon 8 Gen 4 release

The Korean company, along with SK Hynix, wants to be ready by the end of 2024. Samsung and SK Hynix are working together to get a certification on LPDDR6...

www.gsmarena.com

Next-Gen LPDDR6 memory to hit up to 14.4 Gbps data rate, DDR6 up to 17.6 Gbps - VideoCardz.com

LPDDR6 up to 14.4 Gbps, DDR6 up to 17.6 Gbps JEDEC presentation outlines the future of consumer memory standards. The Low Power Double Data Rate 6 (LPDDR6) memory may be introduced with data rates starting from 10.667 Gbps and bandwidth of 32 Gbps. This is the new information coming from the...

videocardz.com

Not before 2025 it seems.

 

[Tuna-Fish]

Isn't that 24-bit width going to be problematic?

That means no more 8 GB, 16 GB, 32 GB,... capacities.

No, again, transfer size is 512 (or 256) bits of data. And 64 (32) bits of metadata, with a burst length of 24.

Found the full slide deck online (maybe it was posted in that Twitter thread but I don't have an account and can't see replies)

Thanks, this is better.

Interesting stuff about the extra bits, though I am less optimistic about ECC being supported since I could easily see the user defined half being used for some type of tagging rather than ECC, and the built-in half being used for lower power rather than link protection.

The most important kind of tagging that is being pushed heavily by both academia and industry right now is CHERI. CHERI requires a single bit per naturally aligned pointer, or, for 64-bit systems, 4 bits per 32B. SECDED ECC for 32B requires 12 bits. The amount of host-defined metadata in this standard is 16 bits per 32B. You can do both.

Edit: 18 GB it is! I forgot that18 GB is possible by using 3x 6 GB chips.

With LPDDR5, the pattern was 8, 12, 16, 24, 32, 48, 64 etc..

With LPDDR6, it will be 12, 18, 24, 36, 48, 72, 96, 144, 192 etc..

No. LPDDR6 CAMM2 has power-of-2 set of chips. (4,8,16). Each line in LPDDR6 subchannel has 272 stored bits, of which 256 are for data. There is no reason why a LPDDR chip wouldn't have a power-of-2 amount of lines. The interface is not power-of-2, but the amount of actual data moved per transfer is.

 

[Glo.]

Just a quick calculation.

If LPDDR6 on LPCAMM allows for 384 bit bus, then with even base LPDDR6 config on 384 bit bus we will get... 500 GB/s bandwidth.

Thats enough to feed a pretty large GPU, CPU and NPU subsystems. Thats large enough bandwidth to compete with highend stuff from Apple.

 

[FlameTail]

Just a quick calculation.

If LPDDR6 on LPCAMM allows for 384 bit bus, then with even base LPDDR6 config on 384 bit bus we will get... 500 GB/s bandwidth.

Thats enough to feed a pretty large GPU, CPU and NPU subsystems. Thats large enough bandwidth to compete with highend stuff from Apple.

That would require two LPCAMM modules, no?

LPDDR6 LPCAMM is 192 bit per module

 

[Glo.]

That would require two LPCAMM modules, no?

LPDDR6 LPCAMM is 192 bit per module

Yep.

 

[FlameTail]

So will LPDDR6 make 192 bit memory bus mainstream?

 

[Doug S]

So will LPDDR6 make 192 bit memory bus mainstream?

Why would you think that? I'm thinking smartphones will go to 48 bit, and standard PCs to 96. Bigger PCs to 192 using two LPCAMM3. Look at how much space 192 bits worth of LPDDR controllers takes on M3 Pro. You think everyone is going to pay that much die area for mainstream PCs? Heck I think we'll see some entry level PCs that have 48 bit wide memory soldered in, not everyone is going to want to pay more for an "AI PC". Some people just want to surf the web and read their email.

Consider that even if DRAM OEMs make x24 DRAMs (I've seen that suggested, have no idea if its true) so that a single DRAM chip can handle an entire LPDDR6 channel that's 4 chips for 96 bits wide. Given that 32 Gb DRAMs are the current state of the art that's presumably what will be used for making LPDDR6 modules (they never make newer standards with older processes) That's 4 GB in a single chip, meaning 16 GB would be the minimum config for an LPDDR6 LPCAMM if it is 96 bits wide.

 

[Glo.]

Why would you think that? I'm thinking smartphones will go to 48 bit, and standard PCs to 96. Bigger PCs to 192 using two LPCAMM3. Look at how much space 192 bits worth of LPDDR controllers takes on M3 Pro. You think everyone is going to pay that much die area for mainstream PCs? Heck I think we'll see some entry level PCs that have 48 bit wide memory soldered in, not everyone is going to want to pay more for an "AI PC". Some people just want to surf the web and read their email.

Consider that even if DRAM OEMs make x24 DRAMs (I've seen that suggested, have no idea if its true) so that a single DRAM chip can handle an entire LPDDR6 channel that's 4 chips for 96 bits wide. Given that 32 Gb DRAMs are the current state of the art that's presumably what will be used for making LPDDR6 modules (they never make newer standards with older processes) That's 4 GB in a single chip, meaning 16 GB would be the minimum config for an LPDDR6 LPCAMM if it is 96 bits wide.

With "AI everywhere" memory capabilities requirements will go through the roof.

Yes, I believe there is no turning back and scaling memory down. It has to scale up, everywhere.

 

[adroc_thurston]

With "AI everywhere" memory capabilities requirements will go through the roof.

Language models don't do anything useful. Come on.

Yes, I believe there is no turning back and scaling memory down. It has to scale up, everywhere.

DRAM scaling died like a decade ago, champ.