Intel presentation at HC this year was a joke. It's very disappointing they let pure marketing presentation happen
Whenever AMD has withheld such [CPU] data within the past decade, it's been a complete disaster on release, and FAR opposite to the forum hype from the year before.What is questionable is your ability to take the numbers for what they are once they are at odd with your IPC "estimations", they could have used Cinebench 11.5 that it would had displayed the same figures, it s just that it would have given more info to their competitor, why should they do so when the latter didnt even disclose their SKL uarch before the last HC, that is, one year after it was released, so much for transparency...
I went looking and it isn't an issue with AVX2. For blender generic build, or 2.77 release,etc. __m256 style instructions aren't used, instead the intrinsics are __m128. If the switch was made we could see up to 30% improvement on the Broadwell-E processor. Which is technically two full refreshes or one new architecture ahead of AMD.How do you know that? The Stilt found that AVX/AVX2 support made no difference in Blender performance on Intel processors.
I went looking and it isn't an issue with AVX2. For blender generic build, or 2.77 release,etc. __m256 style instructions aren't used, instead the intrinsics are __m128. If the switch was made we could see up to 30% improvement on the Broadwell-E processor. Which is technically two full refreshes or one new architecture ahead of AMD.
imho, they should get rid of FMA code for AVX2.
VIA Isiah 2 doesn't support it. Intel & AMD largely execute it slower than Mul+Add.
Hmm. Interesting. Have you been able to test this yourself? I would if I had any Intel chips around, but I don't. Nor do I have Summit Ridge (heh).
What is questionable is your ability to take the numbers for what they are once they are at odd with your IPC "estimations", they could have used Cinebench 11.5 that it would had displayed the same figures, it s just that it would have given more info to their competitor, why should they do so when the latter didnt even disclose their SKL uarch before the last HC, that is, one year after it was released, so much for transparency...
Intel disclosed the SKL micro architecture back at IDF 2015.
That s not the subject but they actually disclosed it only at HC 2016, hence the recent articles on the thing, hardware.fr state that they asked for infos that never come despite promises made one year earlier, so much for your 2015 date.
http://www.hardware.fr/news/14761/hot-chips-m1-sve-parker-info-skylake.html
What do you see on the slide below, HC 2015..?..
https://www.computerbase.de/2016-08/kaby-lake-prozessor-intel/
Of course one does need much effort to imagine what did prompt them to do so..
Nothing that ressemble AMD exhaustive explanation of their uarch, frankly, that s poor, no wonder they got back at HC one year later.
To get back on topic you can see on the slide above that SKL has two 128b/256b FP ports while Zen has four 128b ports, if anything this should be more efficient in legacy SSE, wich is the norm since there s no way that AVX or even FMA can be used for more than little parts of a code.
http://www.intel.com/content/www/us...-ia-32-architectures-optimization-manual.html
More detailed info in the optimization guide that's been out since last year.
Intel presentation at HC this year was a joke. It's very disappointing they let pure marketing presentation happen
Even though I admit having been off topic in my comment regarding Intel HC presentation, I'm certainly no hater/fan of either AMD or Intel, and being accused of that upsets me, but I'll live with thatwhat's questionable is people's inability to keep their usual AMD vs. Intel/nvidia garbage out of this thread.
No need to test it, operands ( not instructions ) are __m128 in source code, so 128bit wide vector code will get generated, either SSE2, with some SSE4 (dot products) or AVX ( with some 128bit FMA3 code ). Not sure why they are not using wider vectors, but could be due to inherent limitations in their data structures.
Still the point stands, it is perfect test case to extract maximum from AMDs 4 mixed FPU pipes, while not stressing data paths beyond 128bits and leaving half of Intel's vector hw idle. Still i am very impressed that they are able to run code like that @ Broadwell speeds at same clock. Intel used to have insane advantage in such code and I know from my work on Skyrim's SkyBoost mod vectorization efforts - SandyBridge was able to chew through code, shrugging penalties for unaligned loads and turning great results.
But in the end all that matters is that x86 dies
If Blender still uses single precision, those 128 bit vectors fit quite nicely, as 4 vector elements are a good base for the typical coordinate transformations using 4x4 matrices. Colors could be represented as RGBA as well.I went looking and it isn't an issue with AVX2. For blender generic build, or 2.77 release,etc. __m256 style instructions aren't used, instead the intrinsics are __m128. If the switch was made we could see up to 30% improvement on the Broadwell-E processor. Which is technically two full refreshes or one new architecture ahead of AMD.
imho, they should get rid of FMA code for AVX2.
VIA Isiah 2 doesn't support it. Intel & AMD largely execute it slower than Mul+Add.
Has this been posted before? Is it reliable?
https://twitter.com/BitsAndChipsEng
"Zen SMT it's more advanced than Skylake SMT, according to several software developers. More info during next weeks. Stay tuned!"
"Zen L3 Cache will be a lot faster than Broadwell-EP/EX L3 Cache!"
"Zen ES currently in the wind are just EVT (Engineering Validation Test) CPUs. The frequencies of final ES will be a lot higher, as we said."
“The key from the beginning was achieving the performance gains while keeping power consumption down, Clark said. With Zen, energy efficiency was going to be just as important as performance”. During the first interview about Zen, Jim Keller said: “We know how to do small dense cores and we know how to do high frequency. What I've asked the team to do is take the DNA from both”.
But, as Clark says, this work is not exempt from risks: “For me, it wasn't the first time, but you don't do it often because it is so daunting. It's going to take a lot of [effort] and time … It comes with a lot of risk”. However, Clark is a veteran. He works at AMD since K5 project.
Last, but not the least, now we know why this new uArch is called Zen: “As the lead [on the core development], I picked 'Zen' as the [codename] because zen is a balance. We needed to balance the whole thing to make it work”.
What AMD need for the moment is not to beat Intel on pure performance, but to be competitive enough on the price/performance/power relationship. If they come in a reasonable distance from Intel offerings and price the parts adequately, they could gain back some market share. I.e. I expect the ST performance to be lower than Broadwell, but if it is not much lower, AND they place their 8 core at a similar/slighly lower price than Intel's 4 core parts, and 4 core dies in competition with Intel's two cores, they will have a good price/perf in MT application (I could dare to say an edge, but it's too ealry to say anything at this moment) while Intel will still rule i.e. gaming or poorly threaded applications. If they want to add too much premium, then it wil lbe a flop. But, nevertheless, I think Zen will definitely improve the situation compared to the present desktop scenario (but that's easy, I suppose).
Relying on price has been AMD's problem. There's a saying in sales - "He who lives by price dies by price".
I don't know how anyone expects AMD to stay in business selling 8 cores at the price Intel sells 4 cores at. Even Lisa Su has publicly stated she wants AMD to stop being the cheap chip company.
I don't think AMD will be able to charge more than around $349 for 8C/16T Zen given the perf/clock and clock speeds. 8C/16T Zen will likely be what AMD positions as the direct competition to 4C/8T Kaby Lake-S. AMD will likely try market it on multi-threaded competitiveness relative to the 7700K.
I dont believe 8C 16T ZEN will compete against Socket 1151 and Core i7 7700K, there will be 4C 8T and 6C 12T SKUs for that segment.
Has this been posted before? Is it reliable?
I guess the folks saying that aren't familiar with the way gourmet is greatly outclassed, in terms of profits, by fast food. Fine wine is outclassed among even adults by soda sales. The Honda Fit sells a lot more and makes a lot more money for its company than a Rolls.Phynaz said:Relying on price has been AMD's problem. There's a saying in sales - "He who lives by price dies by price".
Remember that the chip will be useful for other things like Virtual Machines, giving an edge on that. It can go up 500 dollars at worst and 700 at best.I don't think AMD will be able to charge more than around $349 for 8C/16T Zen given the perf/clock and clock speeds. 8C/16T Zen will likely be what AMD positions as the direct competition to 4C/8T Kaby Lake-S. AMD will likely try market it on multi-threaded competitiveness relative to the 7700K.
I am hearing rumors that zen is on par with kaby lake performance, wow amd does not kid around any longer.
That is supposed to be Zen+, not that Zen. Also After Zen+ , they will go with Starship.I am hearing rumors that zen is on par with kaby lake performance, wow amd does not kid around any longer.
That is supposed to be Zen+, not that Zen. Also After Zen+ , they will go with Starship.