Hi
Can anyone explain how the P4 quad pumped bus works. I can get my head around DDR busses but quad speed is puzzling me?
For example the rising clk edge must be divided into 2 phases eg For a 3V signal, clk1 is during 0 to 1.5V transition and clk2 is during 1.5V to 3V transition. Is this how it works ?, if so how does it manage to achieve all the setup and hold times for the bus devices ?
Regards Geoff
Can anyone explain how the P4 quad pumped bus works. I can get my head around DDR busses but quad speed is puzzling me?
For example the rising clk edge must be divided into 2 phases eg For a 3V signal, clk1 is during 0 to 1.5V transition and clk2 is during 1.5V to 3V transition. Is this how it works ?, if so how does it manage to achieve all the setup and hold times for the bus devices ?
Regards Geoff