POWER6

[Random Variable]

http://www-03.ibm.com/press/us/en/pressrelease/21580.wss

 

[Idontcare]

Pretty darn impressive how little silicon they actually have in the channel on these 65nm SOI devices these days: xtor XSEM from IBM

 

[buddhatb]

Thanks for the article. Pretty impressive CPU indeed.

 

[Maximilian]

I was reading about that earlier, is this the power 6? I dont know the description was chinese or somthing.

If it is the Power6 i have to say i liked the Power5 better because its symmetrical Its obviously not designed for aesthetics but ill never use the thing so ill just judge by looks.

 

[Idontcare]

Originally posted by: Soviet
I was reading about that earlier, is this the power 6? I dont know the description was chinese or somthing.

If it is the Power6 i have to say i liked the Power5 better because its symmetrical Its obviously not designed for aesthetics but ill never use the thing so ill just judge by looks.

That linked photo for power 6 looks like an ancient power 5 prototype.

See here for micrograph of the chip and here for pictures of the packaged chip (pre chip cap attachment).

 

[hans007]

i tihnk the most relevant thing for most of us about the new power 6 is if AMD can somehow leverage that proces technology to make 4+ ghz barcelonas?

I mean the power 6 is similar in die size, and IBM and AMD share fab tech. If amd could somehow make a 4 ghz barcelona, it would be interesting.

 

[Idontcare]

Originally posted by: hans007
i tihnk the most relevant thing for most of us about the new power 6 is if AMD can somehow leverage that proces technology to make 4+ ghz barcelonas?

I mean the power 6 is similar in die size, and IBM and AMD share fab tech. If amd could somehow make a 4 ghz barcelona, it would be interesting.

There is a HUGE difference between a technology node versus a chip design in terms of the operating frequency.

A process node enables xtor switching speeds...true...but the xtor logic (many many xtors involved) determines the operating speed of the device.

IBM could use the same 65nm node that generates 4.7GHz Power6 and create a 10GHz Power7 with 100 transistors and 0.0000000001 IPC (figuratively speaking of course).

Just because process node XYZ enables device ABC to reach clockspeed 4.7GHz does not mean it will enable any other device to reach the same clockspeed...that is up to the xtor logic and IC layout.

For example look at the clockspeed delta between Intel's 90nm x86 XEON chips and their 90nm Itanium chips...same process technology, totally different integrated circuit, wildly different maximum operating frequencies.

 

[Maximilian]

Originally posted by: Idontcare

Originally posted by: Soviet
I was reading about that earlier, is this the power 6? I dont know the description was chinese or somthing.

If it is the Power6 i have to say i liked the Power5 better because its symmetrical Its obviously not designed for aesthetics but ill never use the thing so ill just judge by looks.

That linked photo for power 6 looks like an ancient power 5 prototype.

See here for micrograph of the chip and here for pictures of the packaged chip (pre chip cap attachment).

It looks tiny, whats a chip-cap? Will it make it as big as the power 5?

 

[Idontcare]

Originally posted by: Soviet
It looks tiny, whats a chip-cap? Will it make it as big as the power 5?

The "chip cap" is IBM's version of the IHS.

I don't think it will make final packaged chip as big as the Power5 from those images you linked to but I have no reason to state or beleive this.

 

[nyker96]

man you beat me to it was about to post it ... oh well.

 

[Schmeh]

Originally posted by: Soviet
I was reading about that earlier, is this the power 6? I dont know the description was chinese or somthing.

If it is the Power6 i have to say i liked the Power5 better because its symmetrical Its obviously not designed for aesthetics but ill never use the thing so ill just judge by looks.

The Power 5 image you linked is of a multichip module, not a single Power 5 chip. Each of the four center chips contains 2 Power 5 cores and the outer four chips hold 36MB of L3 cache.

Here is a pic of a single Power 5 die with 2 cores: Power5