Probably, the only reason why intel did it was to win the clock race. After they lost face when athlon beat them to the all-important 1000MHz barrier. I guess we will never know.
That's simply not true...I don't think you appreciate the amount of time it takes to bring a microprocessor from architecture specification to circuit design to the market. I know of a few grad students here that were involved in the P4 microarchitecture spec back in early '96, and the design certainly started in '95...at the time (in '96, certainly when the design goals of the microarchitecture were solidified), IIRC the Penitum MMX was at 200 MHz (maybe 166 MHz?) and AMD had the K5 at 90Mhz. In addition, the latest and greatest Pentium clearly had a large performance lead over every other x86 microprocessor. The K6 and the Athlon simply had no influence on the design of the Pentium 4 microarchitecture. An implication of this is just speculation.
The reasoning behind pushing clock rate in the Pentium 4 was based on a focus on wire delays. In a simplistic view, when a circuit is shrunk with an improvement in lithography technology, transistor delays decrease with respect to the size of the circuit, but wire delays do not. Because of this aspect, wire delays increasingly dominate the delay in a circuit. To combat this tide (which the designers felt would hurt performance), a number of aspects designed to reduce wire delays were incorporated. A long pipeline allows for a better circuit layout and distribution of wire delays; the P4 pipeline allows for two stages that are devoted to propogating signals. The pipelined ALUs, smaller, low-latency L1D cache, and higher-latency complex operations relax their influence they have on the critical path in the microprocessor. There may be arguments against the design decisions that influenced the P4 core, but these
are the technical reasons that influenced the design. I'm sure that the marketing department was not upset about the end result of the P4 design, but it simply did not have an overriding influence on the engineers.
Many people seem to think that Intel first explored this high clock rate/lower ILP path with the P4. This is also simply not true. There have been other points in microprocessor design where new paradigms lead to high-clock rate designs. In the early 90's, microprocessors were beginning to explore dynamic (out-of-order) instruction scheduling and high-issue rates. But dynamic scheduling with high-issue rate has a nearly N^2 complexity relationship with the number of instructions N that are "looked at" each cycle. Early dynamic scheduled designs (MIPS R10000, IBM RS6000) had high IPC, but with the relative inexperience with the design paradigm, clock rate scalability was quite bad. The Alpha EV5 team, which stressed performance above all other factors (power, cost), decided on a simple, high-clock rate design. Where other microprocessors had out-of-order scheduling with 3- or 4-way instruction issue, the EV5 had static (in-order) scheduling with 2-way (integer) instruction issue. Through their architecture decisions as well as innovative circuit design, the EV5 was released at around 500 MHz; the second fastest microprocessor at its release was (IIRC) the 200 MHz HP PA 8000. Despite being clocked 2.5X faster, the EV5 was around 10-20% faster in SPECint, though no one argued otherwise that the EV5 was clearly (and continued to be) the highest-performing microprocessor.
Take another change, IBM's switch to a more automated design (rather than the higher-performing, yet more expensive full custom design) with the POWER4. IBM's reliance on automated design means that when all else is equal, their design will likely not be clocked as high as a full-custom microprocessor design. To combat some of this deficit, the POWER4 has a very long pipeline for a RISC/server class MPU; 14 stages vs. 7 stages on the Alpha EV6/EV7 and 8 stages on the Itanium 2. In addition, despite its higher instruction retire rate compared to many RISC server-class microprocessors, the POWER4's grouping restrictions leads to lower respective performance. In the end, the POWER4 reaches 1.3 GHz at 180nm, compared to 1.15 GHz (EV7) and 1 GHz (Itanium 2) on the same feature size. The POWER4 has a lower ILP, but one cannot deny that IBM's design decisions have lead to one of the highest-performance server microprocessors, as well as excellent compactness of its core that has led to its dual-core designs.
Somehow, I doubt that. If you dig out the benchmarks when the P4 1.4 was released, there were several applications where the P3 actually beat the P4. Running at lower clock speeds. How is it possible the the famed intel engineers didn't notice such a performance hit!!!
Make it a fair comparison. The P3 hit a wall at 1GHz at 180nm, whereas the P4 stopped at 2GHz on the same 180nm process technology. Searching through some SPEC results, the Pentium 3 1 GHz yields 462 in SPECint and 340 in SPECfp (base). The 2GHz P4 (Willamette) achieves 684 in SPECint and 745 in SPECfp, an increase in performance of 48% (SPECint) and 219% (SPECfp) on the same process technology. I don't see that as a mistake by the P4 engineers.
* not speaking for Intel Corp. *