Discussion RDNA4 + CDNA3 Architectures Thread

[DisEnchantment]

With the GFX940 patches in full swing since first week of March, it is looking like MI300 is not far in the distant future!
Usually AMD takes around 3Qs to get the support in LLVM and amdgpu. Lately, since RDNA2 the window they push to add support for new devices is much reduced to prevent leaks.
But looking at the flurry of code in LLVM, it is a lot of commits. Maybe because US Govt is starting to prepare the SW environment for El Capitan (Maybe to avoid slow bring up situation like Frontier for example)

See here for the GFX940 specific commits

History for llvm/lib/Target/AMDGPU - llvm/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - History for llvm/lib/Target/AMDGPU - llvm/llvm-project

github.com

Or Phoronix

More AMD "GFX940" Enablement Work Landing In LLVM - Phoronix

www.phoronix.com

There is a lot more if you know whom to follow in LLVM review chains (before getting merged to github), but I am not going to link AMD employees.

I am starting to think MI300 will launch around the same time like Hopper probably only a couple of months later!
Although I believe Hopper had problems not having a host CPU capable of doing PCIe 5 in the very near future therefore it might have gotten pushed back a bit until SPR and Genoa arrives later in 2022.
If PVC slips again I believe MI300 could launch before it

This is nuts, MI100/200/300 cadence is impressive.



Previous thread on CDNA2 and RDNA3 here

Question - Speculation: RDNA3 + CDNA2 Architectures Thread

Man I have been dying to make this one for a while now. First rumours for RDNA3 are here so new thread time! Just going to start off with this one for now: kopite7kimi on Twitter: "@VideoCardz Ah, I mean a simple mcm design with 10240 cores is not enough. Because the lift from RDNA2 to RDNA3...

forums.anandtech.com

 

[SteinFG]

it goes without saying he's a moron and a waste of time but has anyone looked into mlid's new video about rdna4 or his claims?

last posts are all about the cancelled project leaked by MLID. About the rest of RDNA4 - I don't remember anything, it was super boring.

 

[Timorous]

Correct!
This had CU count in upper 200's and was going to cost you a kidney or two.

So was the cancellelation more to do with hardware implementation or was it more to do with getting the drivers working with current game APIs?

 

[blackangus]

I think it's Intel themselves who have that problem

LOL! Certianly is evident today!

 

[adroc_thurston]

So was the cancellelation more to do with hardware implementation or was it more to do with getting the drivers working with current game APIs?

Both.

 

[Joe NYC]

I think they would use a single N6 die with 2 MCDs + Infinity Cache. with die size of 100-150 mm2

Then they would stack GCD of approximately same size (N5, N4, N3) on top of it. Which would be Navi43 (or Navi53). This part should be bordering non-brainer feasible, even in 2024.

The tricky pat would be to connect multiple of these stacked MCD/GCD combos (2, 3, 4) with extremely high bandwidth low latency link that would also have to be stacked and using Hybrid Bond. I have seen active silicon bridges (in AMD patents) spanning 2 dies, but it is unclear if this technology is feasible.

It could look something like this, it could have potentially only a 3 types of dies (or potentially 4 if they added an I/O die. I think that is the only way would approach competing on highest end, competing with 500-800 mm2 NVidia monolithic GPUs.

View attachment 83643

Seems like I was (mostly) on the money with this diagram.
- GCD (can) become multiple SED (shader engine die). Not sure about the benefit
- my MCD+IC is called AID (active interposer die)
- MID in the picture is what I mentioned as a potential other separate die.

BTW, @DisEnchantment digging up the patents is what lead to my composition above.

Here is what MLID shows as a potential Navi4C.

So, good to keep in mind that AMD is really going for it, it is going cut off NVidia's testicles in client and datacenter GPU the same as it did to Intel in server CPU.

​

 

[adroc_thurston]

- GCD (can) become multiple SED (shader engine die). Not sure about the benefit

Those are naked shader engines backed by L2.

- my MCD+IC is called AID (active interposer die)

Oh it's more than that, trust me.

it is going cut off NVidia's testicles in client and datacenter GPU the same as it did to Intel in server CPU.

Well yea, current Radeon hweng program lead is the Rome/Milan dude; quite the experience in snapping necks thru the wonderful power of silicon spam.
NV is already twitchy about all manners of DC GPU stuff so they're defo doing the right(tm) thing.

 

[Joe NYC]

Those are naked shader engines backed by L2.

Oh it's more than that, trust me.

Seems that way. also, a lot of routing of data.

But for the purpose of building blocks and scaling to make different level SKUs, each one of the AIDs will likely connect to 2 memory channels on both ends.

Do you think that AID can stay on N6 or is it going to be a more advanced process?

Well yea, current Radeon hweng program lead is the Rome/Milan dude; quite the experience in snapping necks thru the wonderful power of silicon spam.
NV is already twitchy about all manners of DC GPU stuff so they're defo doing the right(tm) thing.

Hard to fight silicon spam when you are at the reticle limit.

Even harder when the competition can mix in inexpensive N6 into the spam...

 

[adroc_thurston]

Do you think that AID can stay on N6 or is it going to be a more advanced process?

N6 is the last good node for SRAM spam so like, lol.
What are the other options?

Even harder when the competition can mix in inexpensive N6 into the spam...

It's not inexpensive, still like 9.5k a wafer.
Halo N4x cost to build was something horrendous(ly funny).

 

[Joe NYC]

N6 is the last good node for SRAM spam so like, lol.
What are the other options?

If there are any parts of the GPU that migrated outside of SED, I was wondering if it's something like N5, but I hope not, I hope it can stay on N6

It's not inexpensive, still like 9.5k a wafer.
Halo N4x cost to build was something horrendous(ly funny).

I thought AMD was paying like 7k for N6/N7 wafers.

 

[adroc_thurston]

If there are any parts of the GPU that migrated outside of SED,

They're not the most power-hungry things ever.

I thought AMD was paying like 7k for N6/N7 wafers.

lol nope

 

[Joe NYC]

They're not the most power-hungry things ever.

lol nope

It would not surprise me if others pay 9.5k per N6 wafer, but AMD pays less.

 

[adroc_thurston]

but AMD pays less.

nope.
They pay market prices.

 

[Joe NYC]

nope.
They pay market prices.

BTW, this mysterious tiny COW_L silicon bridge die can open the floodgates of future designs...

I would like to be a fly on the wall, when Intel's Foveros people who go on their typical daily routine of self pleasuring themselves, when Pat Gelsinger storms in the room and screams:
"Is this what you have been doing here for a decade?"

 

[adroc_thurston]

this mysterious tiny COW_L silicon bridge die can open the floodgates of future designs...

well, yea, hello Venice.

 

[maddie]

Reading these latest posts make me laugh at a poster a while back, claiming that chiplets and associated tech was a minor development for computing. If only they knew.

 

[Joe NYC]

well, yea, hello Venice.

It seems it could also obsolete the interposer on future Mi300s, which, by my estimate, could be somewhere between 2,000 and 3,000 mm2

 

[adroc_thurston]

It seems it could also obsolete the interposer on future Mi300s, which, by my estimate, could be somewhere between 2,000 and 3,000 mm2

Well yea that's the idea.
big CoWoS is hard, limited capacity and expensive.

 

[Joe NYC]

Well yea that's the idea.
big CoWoS is hard, limited capacity and expensive.

Seems like a good incentive to get Mi400 out pronto. To bypass the CoWoS capacity constraints.

BTW, silicon bridge, with HB, should also reduce power overhead and allow higher bandwidth.

 

[adroc_thurston]

Seems like a good incentive to get Mi400 out pronto. To bypass the CoWoS capacity constraints.

They're not particularly in a hurry.
MI400 is a big-big change.

 

[Joe NYC]

They're not particularly in a hurry.
MI400 is a big-big change.

There are 2 parts to success:
1. come up with good stuff
2. sell a shitload of it

AMD is quite bad at #2. Needs to improve on it.

 

[adroc_thurston]

AMD is quite bad at #2

They're pretty good at that.

 

[Joe NYC]

They're pretty good at that.

Bronze medal is not bad, but if there are only 3 serious competitors (NVidia, Intel, AMD), AMD needs to aim higher in the quantities of stuff they sell (after they spent all the money on R&D)

 

[adroc_thurston]

AMD needs to aim higher in the quantities of stuff they sell

Depends on what markets do you mean by that.
More client rev means lower laptop APU ASP which is no bueno.

 

[Joe NYC]

Depends on what markets do you mean by that.
More client rev means lower laptop APU ASP which is no bueno.

Total profits are more important that profit margins, more important than ASPs.

 

[adroc_thurston]

Total profits are more important that profit margins

Lisa doesn't think so.

more important than ASPs.

ASPs matter a lot more than you think.