Speculation: Ryzen 3000 series

[Vattila]

Already with their first 7nm products, AMD is embarking on a radical chiplet design methodology for their 64-core "Rome" server CPU (eight separate 8-core CPU chiplets + an IO chiplet in the CPU package). This has left many, myself included, confused about what Ryzen 3000 will look like. I used to think AMD would play it safe with a monolithic approach and simply add a single CCX to their "Zeppelin" die. But now it seems likely that they will reuse their 7nm 8-core chiplet in the AM4 socket as well. But will they use one or two? Perhaps they will use one CPU chiplet plus a GPU chiplet? Or put an iGPU on the IO chiplet? Or perhaps, contrary to current expectations, they have designed a monolithic die for AM4? Perhaps an APU?

Time to have a poll and do some speculation!

PS. Note that the poll is multi-choice. Select all that you think will appear in the AM4 socket. Also note that the poll is about the chip design, not how many cores are enabled or functional in certain SKUs (e.g. initial offering). For example, if you think AMD will use two 8-core CPU chiplets in the AM4 socket, but with only 12 cores enabled (initially), then vote for the 16-core modular design.

 

[Zucker2k]

I went with the 12-Core because that's what I've always believed AMD will need to properly trade blows with the 9900k (in cpu-heavy desktop usage scenarios). Yes, this means the i9 family will retain supremacy in most things single-core to few-cores.

I am hoping AMD does not need a 16-Core chip in the desktop landscape. Such a move would be a tell-tale sign that clocks are far from where they ought to be. If not, why would AMD want to double the performance of the 2700x on the desktop? What about power consumption? I just don't see this happening on the desktop, unless AMD is shooting for that 210W no-holds-barred holy grail.

 

[epsilon84]

I went with the 12-Core because that's what I've always believed AMD will need to properly trade blows with the 9900k (in cpu-heavy desktop usage scenarios). Yes, this means the i9 family will retain supremacy in most things single-core to few-cores.

I am hoping AMD does not need a 16-Core chip in the desktop landscape. Such a move would be a tell-tale sign that clocks are far from where they ought to be. If not, why would AMD want to double the performance of the 2700x on the desktop? What about power consumption? I just don't see this happening on the desktop, unless AMD is shooting for that 210W no-holds-barred holy grail.

I went with 12C as well. 16C for desktop seems too far fetched due to the power consumption, not to mention it will probably break backwards compatability with a lot of mobos, especially the lower end B350/B450 mobos with average power delivery.

 

[maddie]

You're missing a 12C modular.

 

[HurleyBird]

Until recently I was thinking 12 core monolithic. Based on the latest info, probably one (low-mid end) to two (high end) chiplets plus an IO die. How many cores are enabled for the top end part might be lower than the full 16, but I'd guess at >12 to better bury Comet Lake. Could even be 14. But if it really is up to two chiplets + an io die, I'm sure we'll see 16 core SKUs eventually.

 

[Vattila]

To all of you that have voted 12-core monolithic die — note that the poll is about the chip design, not the SKUs. For example, a design may be using two 8-core CPU chiplets, for 16-core maximum, but it may ship with 12 cores functional for certain SKUs (e.g. initial offering). You can change your vote, if you misunderstood.

You're missing a 12C modular.

Do you mean a 16-core design (two 8-core chiplets) with 12 cores enabled? If so, vote for the 16-core modular design.

Until recently I was thinking 12 core monolithic.

I did so too. It seemed the obvious progression — just add a CCX for "Zen 2" and another for "Zen 3". However, now a 8-core CPU chiplet plus IO chiplet with iGPU (i.e. Raven Ridge without the CCX) makes most sense to me. The core war can be fought with the Threadripper platform, especially considering Intel's high pricing. In addition, we will also have the "Picasso" APU, presumably a monolithic 4-core APU on the 12LP process, and presumably part of the 3000 series.

 

[beginner99]

I would for 8-core chiplet design. No need to increase core-count again and it will only canibalize sales of TR3. Plus obvious difficulty with the socket: power delivery and dual-channel for 16 cores? I bet there are enough users that still do not have ryzen and would benefit from a 8-core. Zen2 should offer enough performance increase from IPC and higher clocks. The 16-core parts would then be ryzen 4 or 5-series.

I could imagine for OEM use they put a small iGPU on the IO die. Like really small to drive a display for office and web use and video encode. It wouldn't surprise me but given their cost constraint omitting it seems more likely.

 

[PuchForLife]

I voted 16 core on chiplets. I think AMD is going to fight the core wars on al fronts because that's where they have Intel beaten and with the rumored 15%ipc uplift they'll match Intel in single threaded so increasing the core counts as much as possible is the best way to invalidate most of Intels lineup. i think the 16 core wil have a low base clock to work with the old mobos and something like xfr+ for new mobos that allows it to got to 4,5 ghz on a new mobo. It would also not suprise me that r5 and r3 wil be single chiplets with 6 and 8 cores with r7 being 12 an 16 core. I also think there wil be a 8 core APU with a more biefy 7nm gpu tat wil rival the top i7 in games but with vastly superior onboard graphics for both desktop and laptop

 

[lixlax]

I think the max core count for mainstream desktop is going to be 12 with a chiplet design. The 12 core parts will include 2 chiplets with 6 cores enabled in each (the 16 core parts to follow if Intel gets really competitive or at the latest as part of the Ryzen 4000 series (with Zen 3 cores and 7nm+). Only the 12 core parts will feature 2 chiplets, everything from 4-8 cores would be a IO die plus one chiplet. The max boost/OC in the 4,6-4,8GHz range.

For APU's I predict one chiplet+ IO die+ a GPU die (either 14 or 7nm) or one CPU chiplet+ a 14nm IO die which has a GPU integrated.

 

[tamz_msc]

Mark Papermaster has said that AMD has multiple 7nm designs taped out at TSMC, which includes Vega Instinct MI50/60 and Rome. It is likely that "multiple designs" means more than these two, which could possibly mean that consumer Ryzen 3000 is one of those multiple different designs. Keeping in mind the requirement of low latency in a consumer platform I believe that Ryzen 3000 will most likely be a monolithic 8-core die that foregoes the CCX approach entirely in favor of more tightly integrated cores.

 

[Shivansps]

I think this depends on 2 things:

1) AMD can get the suficient 7nm capacity to produce both monolithics and chiplets Zen 2? Because on Ryzen they just produced 1 CPU and 1 APU. They would now need to produce 1 CPU Monolithic + 1 APU monolithic + CPU Chiplets.

2) They have enoght physical space on AM4 to fit an I/O die with 3 IF + 3 Chiplets? And i say 3 chiplets because with just 2 i think you would be better off with monolithic designs.

 

[Zapetu]

I was thinking about doing a similar poll but this one covers most of the options. There are still a few options that I would like to add to that list. The basic idea behind them is that there would be another 7nm chiplet that would have two DDR4 memory controllers on-die and all the other IO related stuff (PCIe, USB, SATA, etc.) would be located in a smaller IO die. There might even be a small iGPU there (but I'm leaving it out for now).

• 16-core modular CPU+IMC (one 16-core CPU chiplet with 2xDDR4 + a smaller IO chiplet)
• 12-core modular CPU+IMC (one 12-core CPU chiplet with 2xDDR4 + a smaller IO chiplet)
• 8-core modular CPU+IMC (one 8-core CPU chiplet with 2xDDR4 + a smaller IO chiplet)

There might be a better way to describe these options but you all get the idea. I have studied both Summit Ridge and Raven Ridge die shots for a while now and the two DDR4 memory controllers take about 15 to 16.5 mm² of die space (on 14nm) and the part of the SDF (Scalable Data Fabric) that AMD labeled 'IF clock domain' in their IEEE paper "Zeppelin: An SoC for Multichip Architectures" is about 12.5% of the total die space of the Zeppelin SoC (calculated using histogram view of the die shot marking areas with different colors). Thats about 26.7 mm² ("overrounded" up) of the total die space of 212.97 mm² Zeppelin die. And that part very likely does scale with 7nm while the actual DDR4 PHYs might not scale almost at all.

So all in all, let's say that two DDR4 PHYs will take about 17 mm² and IF fabric stuff realated to memory controllers will scale with factor of 2x which gives us 13.25 mm² and a total of 30,35 mm² but let's just be fair and give it 33 mm². Now taking the 72 mm² 8C chiplet and adding those memory controllers to it would give us 105 mm² chiplet with 8 cores and two integrated memory controllers. Adding more CCXs would make IF more complex but each new 4C CCX would be about 25 to 35 mm² more. Let's just go with 35 mm² and call it a day. Please note that while these calculations are based on real die shots of Summit Ridge / Raven Ridge, there's still a lot of speculation here. So the final die sizes would be, give or take:

• 16-core modular CPU with IMC - 175 mm² chiplet (7nm)
• 12-core modular CPU with IMC - 140 mm² chiplet (7nm)
• 8-core modular CPU with IMC - 105 mm² chiplet (7nm)

So with this approach AMD could save few 10 mm² of valuable 7nm die space compared to full monolithic die. Here's a list of pros and cons of this design that i came up with (please speculate and add your own views):

• (+) Memory access latencies would be lower than with "pure" chiplet design
• (+) Smaller 7nm die size than a full monolithic chip
• (+) Little cheaper to develop (compared to monolithic) as only memory controllers need to added to Rome chiplet design and all other IO stuff could remain on a small 14nm IO die
• (-/+) Manufacturing costs might be about the same or only a little lower than a full monolithic design (because of MCM) - would still save 7nm die space
• (-) Design costs would be higher than just going with existing Rome chiplets
• (-) Only one chiplet could be used for Ryzen 3000 (AM4) because of the IMCs
• (-/~) Threadripper could have an option to use two of these chiplets but there would be an IO chiplet between them and therefore memory access would be bifurcated (maybe even more than currently)
• (-/~) PCIe latencies would be higher than monolithic design but it might not matter all that much
• (-/~) Next gen memory (DDR5) would need a new chiplet design but that might also not matter that much since Zen3 will in any case need a new chiplet - still would loose some flexibility while gaining better memory acccess latencies

So that's the idea I've been contemplating in my head for a couple of weeks now but it's a totally another story what AMD has actually done at least for the first few Ryzen 3000 models.

If you have any ideas or suggestions about this approach, please share them with us. Thanks.

Edit: As you can see, I didn't vote for the design presented in this message and this is just an option for a monolithic design while saving few 10 mm² of die space. Would this be worth over similar monolithic design, I don't know for sure. The pure chiplet design has many (manufacturing and flexibility) benefits over this one, though, if we can get over some latency penalties which may not matter that much anyway.

 

[Zapetu]

I think this depends on 2 things:

1) AMD can get the suficient 7nm capacity to produce both monolithics and chiplets Zen 2? Because on Ryzen they just produced 1 CPU and 1 APU. They would now need to produce 1 CPU Monolithic + 1 APU monolithic + CPU Chiplets.

Ryzen CPUs use the exact same design than EPYC with Zeppelin dies and there is a lot of stuff that is not needed for desktop. That is all going to move to the IO die on Rome so the 8C core chiplets willl be very pure CPU units without almost any overlapping features. They could be used for almost anything including PS5/XBTwo if Sony/MS chooses to do so.

Monolithic design would tie all IO stuff to one piece of silicon and there's a lot less flexibility. Since memory access latency seems to be the main concern, AMD could go with another chiplet design in the future with just memory controllers on-die. There are many options to choose from.

Mobile APU is a different story (monolithic design would be best utilized there) and as far as I know, they're going with 12nm Picasso first.

2) They have enough physical space on AM4 to fit an I/O die with 3 IF + 3 Chiplets? And i say 3 chiplets because with just 2 i think you would be better off with monolithic designs.

There is room for two 8 core chiplets and an IO die (on AM4) but not for three 8 core chiplets and an IO die but I guess, that's not what you were asking. AMD could also make 4 core variation of their chiplet and put those on the AM4 package. But if they would have chosen that option then maybe they would have used those 4 core chiplets on Rome too.

With two 8C chiplets and an IO die approach AMD can just leave one chiplet missing or replace it with dummy one but that would make thermal characteristics little lopsided (might not matter). They could also go with these two options:

• 16-core modular CPU (two 8-core CPU chiplets + IO chiplet)
• 8-core modular desktop APU (one 8-core CPU chiplet + IO chiplet with a small iGPU (mainly for Ryzen Pro))

I haven't voted yet but those are my current most likely options.

Edit: I did vote but didn't add the "4-core monolithic APU" option yet even if I think that Picasso would be just Raven Ridge on 12nm (with some minor improvements). If I were too pessimistic, I could have also chosen "8-core monolithic CPU" for rebranded Pinnacle Ridge for 8C and below. I still like the idea of an IO die with a small iGPU for Ryzen Pro and all 8C and lower desktop models. Even if you have a dGPU, a small iGPU wouldn't waste that much die space.

 

[moinmoin]

Since Intel appears to be predictably moving to 10c 20t in mainstream I fully expect AMD to have prepared a rise in cores of their own. 16-core modular CPU (two 8-core CPU chiplets + IO chiplet) with the resulting flexibility is the logical next step for AMD considering the full on move to chiplets in Rome.

OT: Since the forum update I'm no longer getting alerts anymore for new threads in watched forums. Anybody else having having this issue and how to fix it?

 

[Fanatical Meat]

Off topic,

I'm looking to build a new machine next year is it a reasonable expectation for these chips to arrive in April or May?

 

[Zapetu]

Off topic,

I'm looking to build a new machine next year is it a reasonable expectation for these chips to arrive in April or May?

Computex 2019 is May 28 - June 1, 2019 so I wouldn't expect (possibly 12C/16C Ryzen 3000 and/or 16C/32C TR3k) availability until Q3 2019. 8C parts (on 7nm) may be released even later, we don't really know for sure. I'm sure we'll know more along the way.

Lisa Su will give her keynote on 7nm CPUs and GPUs at CES 2019 (January 9, 2019).

 

[Shivansps]

Ryzen CPUs use the exact same design than EPYC with Zeppelin dies and there is a lot of stuff that is not needed for desktop. That is all going to move to the IO die on Rome so the 8C core chiplets willl be very pure CPU units without almost any overlapping features. They could be used for almost anything including PS5/XBTwo if Sony/MS chooses to do so.

Monolithic design would tie all IO stuff to one piece of silicon and there's a lot less flexibility. Since memory access latency seems to be the main concern, AMD could go with another chiplet design in the future with just memory controllers on-die. There are many options to choose from.

Mobile APU is a different story (monolithic design would be best utilized there) and as far as I know, they're going with 12nm Picasso first.



There is room for two 8 core chiplets and an IO die (on AM4) but not for three 8 core chiplets and an IO die but I guess, that's not what you were asking. AMD could also make 4 core variation of their chiplet and put those on the AM4 package. But if they would have chosen that option then maybe they would have used those 4 core chiplets on Rome too.

With two 8C chiplets and an IO die approach AMD can just leave one chiplet missing or replace it with dummy one but that would make thermal characteristics little lopsided (might not matter). They could also go with these two options:

• 16-core modular CPU (two 8-core CPU chiplets + IO chiplet)
• 8-core modular desktop APU (one 8-core CPU chiplet + IO chiplet with a small iGPU (mainly for Ryzen Pro))

I haven't voted yet but those are my current most likely options.

Edit: I did vote but didn't add the "4-core monolithic APU" option yet even if I think that Picasso would be just Raven Ridge on 12nm (with some minor improvements). If I were too pessimistic, I could have also chosen "8-core monolithic CPU" for rebranded Pinnacle Ridge for 8C and below. I still like the idea of an IO die with a small iGPU for Ryzen Pro and all 8C and lower desktop models. Even if you have a dGPU, a small iGPU wouldn't waste that much die space.

Ok lets see the options here then:

1- Monolithic 4C APU, for low end desktop and mobile, maybe rebranded RR.
2- 8C chiplet + Dummy
3- 2x 8C chiplets
4- 8C chiplet + GPU chiplet

I dont think AMD would make different core count chiplets, so if its 8C they all will be 8C.

 

[Zapetu]

I dont think AMD would make different core count chiplets, so if its 8C they all will be 8C.

Well for a monolithic design or a chiplet with integrated memory controllers 12 cores would be the most balanced choice, in my opinion. But as I have voted, using two 8C chiplets and a quarter IO die looks like the easiest and most likely option right now. 12C/16C for AM4 seems a little high though but there's nothing wrong with that approach. If the pricing is right there's market for those too.They can easily go up to 48 or even 64 cores on TR3k if they later choose to do.

 

[firewolfsm]

The primary benefit of using the 8 core chiplets is avoiding another mask, but the smaller IO die requires another mask anyways. They could design a monolithic 12 core chip anyways, which would simplify manufacturing and lower costs for AMD. If they want to jump straight to 16 cores, then they might benefit by avoiding having such a large chip, and stick to the chiplet design.

 

[NostaSeronx]

My guesses for AM4 3000s:
8-core Monolithic CPU SoC => Matisse (12LP+)
4-core Monolithic APU SoC => Picasso (12LP+)
16-core Chiplet CPU => Vermeer (7FF) <-- Same I/O chiplet as Renoir
8-core Chiplet APU => Renoir (7FF) <-- Same I/O chiplet as Vermeer

12LP+ => 3x00
7FF => 3x50
Something of the above.

 

[gorobei]

Jim from AdoredTV has a video up on amd's possible future. https://www.youtube.com/watch?v=qgvVXGWJSiE
the main theory is that the i/o die is designed with multiple memory controllers and symmetrical in both axes so that it can be chopped into up to 4 sub dies for use in ps5, apu, ryzen, tr, or epyc. doing so allows them to have way higher yield and bin for speed for way better performance. it also allows them to use gf so the wsa isnt an issue.

he is firmly in 'no more monolithic' camp, so maybe the apu will be a hades canyon type setup on infinity fabric.

 

[Elfear]

I went with the 12-Core because that's what I've always believed AMD will need to properly trade blows with the 9900k (in cpu-heavy desktop usage scenarios). Yes, this means the i9 family will retain supremacy in most things single-core to few-cores.

Based off of Anandtech's Bench comparo, the 2920X (12C/24T) is currently at 92.4% of the performance of a 9900k overall. That breaks out to 89% for gaming and 97% for non-gaming benchmarks. Are you anticipating the performance increase of 7nm Ryzen (IPC + clocks) to be only 8%?


Regarding the probable design of the 3000 series, I'm torn now. I was leaning towards a monolithic design but I'm getting swayed more and more to a chiplet design. If it is a chiplet design, I hope AMD has overcome any latency issues since that will be an important feature for gamers.

 

[HurleyBird]

New AdoredTV video on the topic just came out, still watching:

https://www.youtube.com/watch?v=PCdsTBsH-rI

 

[gorobei]

New AdoredTV video on the topic just came out, still watching:

https://www.youtube.com/watch?v=PCdsTBsH-rI

if the 5.0 ghz stuff is true this could be the straw that breaks the camel's back, the navi stuff would be a hard play for marketshare.

 

[Maxima1]

if the 5.0 ghz stuff is true this could be the straw that breaks the camel's back, the navi stuff would be a hard play for marketshare.

If they don't have a monolithic design, it's virtually certain that this will be true. They can bin much better and segment the fastest chips into the higher core SKUs.