Speculation: Ryzen 3000 series

[maddie]

Why would AMD want to invest any money into porting Dali features over to Stoney? Is there some massive high-margin untapped market there?

As an aside, what does low cost have to do with low margins? It might be difficult, but it's not impossible to have both factors in play.

 

[amrnuke]

There is a big market, yes.

Where can I read more about where the market is for Stoney?

Raven2/Dali on 14nm = 150 mm2
Stoney on 28nm = 125 mm2

Getting rid of negatives of the 28nm node with a transition is ideal.

Stoney's successor would thus be on 22FDX/12FDX have a sub-cm2 die w/ high production quantity compared to Raven2/Dali.

Features gained but aren't included with Raven2/Dali:
- Higher CPU GHz(Excavator is on 28nm, all nodes in 14nm generation are faster, so clock rate intrinsically goes up)
- Access to 64-bit LPDDR4X, and do to timing of launch possible upgradability to LPDDR5 later. (Super-Combo Interface: DDR54/LPDDR54X)
- Smaller die size, higher production capacity(intrinsically lower costs/maturer production line), higher yields, etc.
- 125*C operation support, w/ 150*C 12FDX-HiTemp later on.
- Space/HighTude operability
- Support of a true FIVR do to planar node, reducing mobo costs.
- Longer supported node increasing 10 year support to the absurd 25 year support.

IoT/SBC -> Embedded -> Mission-critical -> Laptop -> AiO -> Credit-card NUCs

However, Stoney on 14LPP-derivatives/12FDX-derivatives => not the goal
Something that does low-cost better and doesn't reduce the latest Zen's cost is preferable.
It also needs to be unrushed, allowing for extended optimization over time. For 22FDX, 22FDX+, 22FDX++, 22FDX#, 22FDX#+, 22FDX#++, 22FDX##, etc. Which might included upgraded substrates(Al2O3), gates(Full metal gate), BEOL(carbon doped copper, CNTs, Nanosheet copper, etc), process(new machines), etc.

What does this have to do with my question?

 

[NostaSeronx]

Where can I read more about where the market is for Stoney? What does this have to do with my question?

I'll get right to finding you that research study on Stoney. Like right this instant, *wheeze*.

Stoney is on 28nm, Raven2/Dali is 14/12nm. It is pretty favorable that from a port of Stoney to all the way to a revolutionary design. In turn, would exceed the design aspect of having a huge 150mm2 die for budget.

Bobcat = 74 mm2
Jaguar = 107 mm2
Zen = 150 mm2
^-- this is the wrong direction for a budget APU.

With that the design choices of Raven2(3200u)/Dali(3020e-3250u)@a LVM Fab compete with the design choices of Renoir(4300u-4800u)@a HVM Fab.

 

[Hitman928]

I'll get right to finding you that research study on Stoney. Like right this instant, *wheeze*.

Stoney is on 28nm, Raven2/Dali is 14/12nm. It is pretty favorable that from a port of Stoney to all the way to a revolutionary design. In turn, would exceed the design aspect of having a huge 150mm2 die for budget.

Bobcat = 74 mm2
Jaguar = 107 mm2
Zen = 150 mm2
^-- this is the wrong direction for a budget APU.

With that the design choices of Raven2(3200u)/Dali(3020e-3250u)@a LVM Fab compete with the design choices of Renoir(4300u-4800u)@a HVM Fab.

Now compare the R&D, verification, and validation costs of developing a 14 nm or 7 nm Stoney CPU as well as mask set costs, assembly and packaging costs, App. engineer costs, and sales/marketing costs against the profit amount from a low value product.

Then take that number and use it to determine the opportunity cost of developing and supporting said product versus using throwaway and scaled down Zen and instead spending the money for more for R&D on high value GPUs, CPUs, increased sales and marketing for said products, increased application engineer budgets to better support high value enterprise customers thus increasing market penetration in high margin markets, increasing TAM, and increased research into distant but critical tech paradigm shifts in process and design tech.

How does the comparison look then?

 

[NostaSeronx]

How does the comparison look then?

Very much in favor for 22FDX/12FDX/7FDX and a conversion of a High Performance @ Server architecture to a Ultra Low Power @ Client architecture. Current RDNA is only the high-performance GPU arch, there is still a Ultra-low-power GPU architecture as well.

 

[Hitman928]

Very much in favor for 22FDX/12FDX/7FDX and a conversion of a High Performance @ Server architecture to a Ultra Low Power @ Client architecture. Current RDNA is only the high-performance GPU arch, there is still a Ultra-low-power GPU architecture as well.

What ultra low power GPU architecture are you referring to?

 

[NostaSeronx]

What ultra low power GPU architecture are you referring to?

It appears with these three:
=> high performance GPU
=> ultra low power GPU
=> machine intelligence

Going into depth and searching for ultra-low-power GPU. It is potentially RDNA w/o 1-cycle Wavefront64 and reduced cache sizes. Basically, making it almost a Wave32 GCN, other than it keeps the register cache in the patent.

 

[Hitman928]

It appears with these three:
=> high performance GPU
=> ultra low power GPU
=> machine intelligence

Going into depth and searching for ultra-low-power GPU. It is potentially RDNA w/o 1-cycle Wavefront64 and reduced cache sizes. Basically, making it almost a Wave32 GCN, other than it keeps the register cache in the patent.

So nothing but wild speculation, got it.

 

[amrnuke]

So nothing but wild speculation, got it.

That's nearly every post. He gives an evasive answer to pointed questions, then spouts a bunch of fantasy about purported architectural advantages of his dream project, under the assumption that he knows more about SoC and chip development than a company full of microprocessor experts and engineers, and more about areas of potential profit than folks with MBAs and decades of industry experience, and to top it all off, led by someone with a PhD in electrical engineering from MIT.

But clearly even with all that experience and education and expertise, AMD are missing a massive, easily exploitable market and making a big mistake.

 

[NostaSeronx]

AMD 3020e should be the R1000's R1102G(2c/2t--6w part--1.2ghz_base). So, there should also be a higher end e-suffix which is based on the R1000's R1305G(2c/4t--8w part--1.5ghz_base).



Best 8W(Dali-RV2) vs Best 15W(Picasso-RV2)

=> https://www.amd.com/en/products/apu/amd-ryzen-3-3250u (95c max temp 15w Dali-RV2)
and https://www.amd.com/en/products/apu/amd-ryzen-3-3200u (105c max temp 15w Picasso-RV2)
Doesn't appear to have any major frequency CPU/GPU/Mem changes from R1606G. Max temp change implies the 3250u might have been tweaked to sustain boosts longer.

 

[Panino Manino]

In case someone missed: https://pc.watch.impress.co.jp/docs/column/semicon/1236258.html

 

[NostaSeronx]

In case someone missed: https://pc.watch.impress.co.jp/docs/column/semicon/1236258.html

I feel that there is something wrong with this slide:

https://pc.watch.impress.co.jp/img/pcw/docs/1236/258/photo007_o.jpg

It is suppose to be for AMD Zen:
StdCell 9-track as 78CPP is only available to 9T High-Density
Cu Metal Layers isn't 11-layers w/ MIM it is 12 w/ MIM.

Zen2 is definitely on HPC.
1x Metal Pitch of 7nm is 40nm. While, the M1 pitch is definitely 57Mx if it was Mobile. Since, Zen2 is HPC it should actually be;
7.5T Std Cells
64CPP
M1 is 64Mx being as it is paired to CPP.

What a big oof on AMD's part.

 

[amd6502]

https://pc.watch.impress.co.jp/img/pcw/docs/1236/258/photo003_l.jpg

Nice find from Panino

It surprises me how large the branch prediction unit is (as well as the decode) and how tiny the area for ALU.

Doesn't surprise me how huge the doubled up FPU is though.

Sadly, my guess for the functional units is way off.

I wonder if the layout for Zen3 will be radically different.

 

[Panino Manino]

@amd6502
I found nothing. I had seen this somewhere else yesterday and today WikiChip wrote about: https://fuse.wikichip.org/news/3320/7nm-boosted-zen-2-capabilities-but-doubled-the-challenges/

 

[Vattila]

Zen2 is definitely on HPC.

Well, WikiChip repeats and elaborates on the 6T claim. I know it was widely presumed that Zen 2 would use the N7 HPC variant (7.5T), but if AMD's slide is correct, that is not the case. Has AMD made a statement elsewhere?

Edit: 6T is also in this slide, so it is very unlikely to be a mistake.

 

[NostaSeronx]

Has AMD made a statement elsewhere?

AMD confirmed and only used 9-track std. cells for Zen/Zen+.
AMD leaked out info of using TSMC's 7.5T w/ 64CPP. (Tom's hardware even did a hit on AMD/TSMC for Zen2(7nm/7.5-track) having less density than Intel Sunnycove(10nm/6.2-track).)

Basically, AMD went for performance(higher Fmax) w/ Zen2(64CPP/44Mx(1.1x HPC pitch)). Which leads into Zen3 being power-optimized(lower power at higher Fnom):
57CPP/40Mx(1.0x mobile pitch, not M1) ((if 6nm)) or 54CPP/36Mx(new 1x and new M1 pitch) ((if 7nm+)).
I believe the new tapeout option for 6nm has M1 similar to 7nm+(only applies to Logic cells) but it is 38nm. The main benefit of 6nm is designers don't need to re-do AMS/SRAM designs.

 

[Vattila]

AMD leaked out info of using TSMC's 7.5T w/ 64CPP. (Tom's hardware even did a hit on AMD/TSMC for Zen2(7nm/7.5-track) having less density than Intel Sunnycove(10nm/6.2-track).)

So that was all wrong then, since AMD now clearly states that they chose the high-density 6 track library (N7 HD) for Zen 2, rather than the high-performance 7.5 track library (N7 HP a.k.a. N7 HPC).

 

[NostaSeronx]

So that was all wrong then, since AMD now clearly states that they chose the high-density 6 track library (N7 HD) for Zen 2, rather than the high-performance 7.5 track library (N7 HP a.k.a. N7 HPC).

Nope, the slides are wrong. 6-track is the Mobile library, there is also no relaxed BEOL for it. TSMC doesn't do custom nodes like GlobalFoundries.

N7 Mobile is always 57CPP, 40Mx, 6T.
N7 HPC is always 64CPP, 44Mx, 7.5T.

Time constraints with Zen2 taping out before those were expanded by third-party EDA makes it even less so. Work starts at 0.5 Risk Production, not fully mature 1.0+ w/ third-party standard cells.

 

[Vattila]

Nope, the slides are wrong.

Highly unlikely. Note that the last slide I posted says that the 6 track library choice enabled additional leakage savings. That is the opposite of choosing a high-performance library with more tracks, which inherently has larger leakage.

 

[NostaSeronx]

Highly unlikely.

Very likely. This work has 3/10ths the amount of authors from the previous architecture(Zen) paper.

Excavator = ~12 authors
Zen = ~10 authors
This work = ~3 authors (previous Zen2 hot chips had ~5 authors)

The fact is that it is already plagued with errors with Zen. Zen isn't 10.5T or 11+MIM, it is 9T and 12+MIM. Which sets the standard that most of the Zen2 stuff is probably wrong as well.

10.5T/9T to 6T would give a lot more Cac improvement than shown. However, 9T to 7.5T is well within physics with the results given.

Note that the last slide I posted says that the 6 track library choice enabled additional leakage savings. That is the opposite of choosing a high-performance library with more tracks, which inherently has larger leakage.

AMD didn't go 9-track to 9-track, they went to 7.5-track which has additional leakage savings over if they did go 9-track.
GlobalFoundries' HPC was 9-track. While, TSMC's HPC is 7.5-track. The benefit of TSMC option is it is in between GloFo's 7SOC(6T) and 7HPC(9T). Lower leakage than 9-track, and higher performance than 6-track. Guaranteeing the design can achieve >4 GHz w/ less mature tools w/o sacrificing density.

 

[itsmydamnation]

am i out of touch? no its the people who made the chip that are wrong! /skinner

 

[NostaSeronx]

Just saw this: https://www.dfi.com/product/index/1455#overview

GHF51ï½AMD®ï½Industrial Motherboardsï½DFI

GHF51, 1.8" SBC with AMD Ryzen⢠Embedded R1000 Series, designed with AMD Ryzen, Pi size, Ubuntu-certified which is ideal for robotic arms/Vehicle Surveillance S

us.dfi.com

1.8 inch SBC w/ 12W Raven2(R1606G/R1505G) and at most 10W Dali(R1305G/R1102G)


^ click for full res

 

[amd6502]

So I guess AMD is putting minimal focus on low end. This means minimal product development and new R+D on lower end products. They are still riding 2c/2t Stoney surprisingly, and then Raven2 will be set to handle the low end all by itself. By then they may have tweaked the 12nm die such that they get cTDPs of 6w-10w.

They can save the worst dies for when Stoney has been completely retired and its dies out of stock. Then release these as 6-10w 1c/2t E-series.

Saving on investing R+D on the low margin low end is a good medium term decision from Su. They can ride these savings for a few years.

But after some time (years) a new low end core will have to be put on the market. So probably this is right now in the concept stage.

 

[VirtualLarry]

After using a budget "Ematic" laptop (Walmart house brand) for a few weeks, and even after adding a USB2.0 AC wifi adapter, because the onboard wifi simply wouldn't even work right,, with either of my routers, I have to say, semi-conclusively, Stoney Ridge SUCKS. It seems to be wholly unable to Skype and web browse using Firefox Nightly 64-bit at the same time, efficiently. Something that even Bay Trail N2830 dual-core Atom CPUs CAN DO.

The A4-9120e 6W APU w/Radeon 3 graphics, just doesn't work all that well. 4GB RAM, 64GB eMMC (kind of a slow one). BIOS allocates 80MB for VRAM, I changed that to force 256MB of VRAM allocation. That seems to help, slightly, with Skype.

If I'm ONLY web-browsing, it's kind-of OK, if you're REALLY PATIENT waiting for page to load, but other than that... the Intel 4205U Celeron 1.8Ghz Lenovo S145 laptop I picked up for twice the money, with 4GB RAM and a real 128GB SSD, is WORLDS BETTER.

The Stoney, sometimes gets in a "mood", and maxes out at 53% CPU used across both cores, and 0.80Ghz max clock. Guess passive cooling isn't good enough?

 

[moinmoin]

So I guess AMD is putting minimal focus on low end. This means minimal product development and new R+D on lower end products.

I don't know, Dali is honestly already more than I expected after they took their sweet time with it. Eventually Dali will be replaced by a 7nm part based on Renoir, possibly 4c then since 7nm density allows that while still making the die smaller. Then they could eventually add a sub-Dali 7nm part, significantly smaller and 2c. But it's clear those are on the very bottom of the whole food chain on a given node, so we will likely be well into the Zen 3 or even Zen 4 gen when those appear.