Speculation: Ryzen 3000 series

[Hitman928]

To summarize my interpretation: The Ryzen 3 series uses the EPYC chiplets and a cut down version of the EPYC IO chiplet. The current 8 cores may end up being 8/12/16 depending on heat and power draw. The IPC is better, at least 10% more likely 15-17%. The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4. The current power draw is almost half of Intels 9900k, but at what speed ? (125 vs 75, where 67.5 is half)

Sound about right ?

moinmoin covered the IO die, but IPC and clocks are still up in the air as it's the combination of the two that lead to performance.

By my calculations, if the Ryzen was running at 4 GHz, then the IPC uptick would be ~15% (for this workload). If the chip was running at 4.4 GHz, then the IPC is only about 5%. I expect the truth lies somewhere in the middle (i.e. IPC up 10% and clocks at ~ 4.2 GHz). Based upon power use, it seems that there's a little more potential for AMD to still increase clocks.

 

[PotatoWithEarsOnSide]

Or they took a cherry-picked, top binned ES 8C chiplet and used it for this preview.

I don't think the price segmenting will be affected by whether it's a fully functional 8C or two partially disabled chiplets, but rather its actual performance.

Whilst I see where you are coming from, I think it would be incredibly deceptive of AMD to use a cherry picked ES 8c for their demo if their intent was for 8c SKUs to be salvaged from 2 defective chiplets. That was something that had been suggested as a possibility given that Epyc 2 and Threadripper would likely consume all of the fully functional 8c chiplets. Hence my incredibly high yields comment.
I don't think that AMD would have done anything intentionally deceptive at their first CES Keynote ever. Given their apparent superiority across the entire product range, I doubt that they'd even need to either.

 

[PeterScott]

The other big takeaway was that 8c is in fact a fully functional chiplet, not 2 defectiv chiplets combined.
It may be that all X class SKUs are like this, and the non-X end up being defective chiplets. Reason being, fully functional 8c chiplet for 8c Ryzen actually suggests incredibly high yields.

I would expect all of the 8C parts to be single die.

I don't get why people think yields are so bad that they would have to resort to using Two half disabled dies.

If you look on the Intel side, Intel went for most of a decade without there ever being a desktop part with disabled dies AFAICT.

This implies that Yields are MUCH better than most people here assume, and that core disabling is done almost exclusively for market segmentation, not die recovery, which is just a small bonus if you already disabling for market segmentation.

 

[PotatoWithEarsOnSide]

I suspect it has more to do with the expected high demand, and their ability to supply enough chiplets. We can't just assume that AMD has enough production capacity with TSMC to meet all of the demand that they'll inevitably have. That's where salvaging comes in. With the core counts being so high, the opportunities for salvaging must exist. Unless there's a penalty for doing so, then why not?

 

[StinkyPinky]

I wonder if having two chiplets increases the latency and therefore impacts certain sensitive processing like gaming.

 

[jpiniero]

So Adored was pretty much completely Fake News, as expected. I do think you will still see a dual die model, but after launch now. Maybe around the time Comet Lake is released.

 

[SPBHM]

the most impressive aspect is the power draw, the performance itself is good, but a 2700x would be able to achieve with around 4.4-4.5GHz, and CB15 has been good to AMD (CMT gains some points over HT) and forgiving to some disadvantages with latency;

if the final part can clock significantly higher than this sample and keep the good power characteristics that's going to be a very good part, but I'm still curious to see how having the memory controller and so on on a different die might affect latency sensitive stuff like gaming for sure.

 

[PotatoWithEarsOnSide]

There's a few sources saying PCIe4 on existing motherboards with Zen 2 CPUs. Only on the nearest slot though, and subject to a BIOS update that AMD may veto.

 

[jpiniero]

I would expect all of the 8C parts to be single die.

I don't get why people think yields are so bad that they would have to resort to using Two half disabled dies.

Because they would want to use the fully unblemished dies for Epyc. But at the same time, 7 nm wafers are expensive so if yields are good enough they can stick with 4/6/8 and then maybe ship a dual die 12 core R9 later.

I'm sure it helps that the launch isn't until June-July.

 

[Shivansps]

More like late Q2/early Q3, probably June. 2H implies as late as December which is too late for Zen2 based on the mid-year release.

For those talking about AdoredTV, I don't see much fundamentally WRONG with what he predicted. The room is there on the PCB for an additional chaplet. That tells us that 16c AM4 chips are possible. AMD just didn't demo one. They also said nothing about clocks. It also tells us that that GPU and GPU+HBM blocks are possible for APUs to come later. The I/O die gives AMD a lot of flexibility.

Lets see, Adored said "cut 1/4 i/o die" that is something he probably pulled out of thin air, someone probably told him about a I/O die or he completely guess it, and thats petty much it. later he corrected himselft and said Ryzen may be completely 7nm (the non I/O die possibility), again false. That I/O die is probably designed for notebooks, desktop and consoles.

The launch date? Fake, the specs and names 100% fake, the prices? fake. He may up correct on the names but thats petty much it. Not to mention the Navi dGPU.

 

[Mopetar]

moinmoin covered the IO die, but IPC and clocks are still up in the air as it's the combination of the two that lead to performance.

By my calculations, if the Ryzen was running at 4 GHz, then the IPC uptick would be ~15% (for this workload). If the chip was running at 4.4 GHz, then the IPC is only about 5%. I expect the truth lies somewhere in the middle (i.e. IPC up 10% and clocks at ~ 4.2 GHz). Based upon power use, it seems that there's a little more potential for AMD to still increase clocks.

Since AMD did indicate that the clocks aren't final, I'd guess that the results we see hint at the IPC gain being reasonably good. They're probably close to the final clocks and I suspect that they picked a value to show off the efficiency gains. They probably only need to add another 100 - 200 MHz to wind close to the same power draw as the 9900k.

You have to bet that they grabbed their best possible binned chip for this comparison as well so they probably don't want to promise exact characteristics at that point.

 

[IEC]

From AnandTech's article:


That's a pretty huge improvement over my R7 1700, at roughly the same chip power...

1421 or so for R7 1700

That's a 44.7% improvement in MT score.

Granted, this is probably the best-case scenario benchmark for them, but with final clocks yet to be decided it will likely only go up between now and release, representing the kind of generational leap we've been missing for a while.

It's great to have competition again.

 

[somethingclever]

They might even hold off on launching anything above 8 cores initially. If supplies are tight, they might be able get more value out of using two 6-core dies to sell two CPUs instead of combining them into a single CPU.

It really depends on balancing wafers from TSMC against GF due to the WSA changes. If they're using extra wafers at TSMC for Vega/Navi production, then they probably don't care about having to use extra IO dies.

I would expect all of the 8C parts to be single die.

I don't get why people think yields are so bad that they would have to resort to using Two half disabled dies.

If you look on the Intel side, Intel went for most of a decade without there ever being a desktop part with disabled dies AFAICT.

This implies that Yields are MUCH better than most people here assume, and that core disabling is done almost exclusively for market segmentation, not die recovery, which is just a small bonus if you already disabling for market segmentation.

I think everyone's forgetting that there's two aspects to binning. First is disabling features that didn't come out right such as cache area/cores/etc. The second is power/frequency characteristics.

AdoredTV said, and I would agree, that AMD is likely reserving the most efficient chiplets for EPYC, and the highest frequency ones for TR.
It could be that AMD would be using half-disabled chips to fit chips that have functioning cores, but low efficiency into Ryzen.

However, i don't think we have enough information on yields and power/frequency to be able to say whether AMD is using 4 core chiplets in Ryzen 8C. Does anyone know how mature TSMC 7nm is?

From Ryzen 1k and 2k, we know the yields are probably going to be high enough to save us from a 2*2C Ryzen.

 

[CHADBOGA]

It is good to see AMD continue to make strides on the CPU front, but they seem to be less capable on the GPU front these days, just when Nvidia is running riot on their pricing.

 

[Abwx]

. I expect the truth lies somewhere in the middle (i.e. IPC up 10% and clocks at ~ 4.2 GHz). Based upon power use, it seems that there's a little more potential for AMD to still increase clocks.

At 15% higher IPC and 25% higher frequency than a R7 1700 (44% higher score) it would consume 15% more power, but here it consume the same at said 44% higher throughput, this is possible by downscaling the (supposedly 4GHz) frequency by 4.4% but then IPC should be 20% higher than Zen 1..

Considering that getting 25% better perf fom 7nm at isowatt and at 3.2 to 4GHz is quite unlikely this point to IPC being the main, if not only, factor in AMD displayed perf improvement, the 1.25x better perf at isowatt was stated for Epyc at much more favourable frequencies than the ones at play here.

 

[rbk123]

The clock speed seems to be in question, but most likely is higher than Zen+ 2000 series in the area of 4.7 maybe more in the final, but at least 4.4.

You're the only one in this thread that thinks the clock was that high. Your low end is even higher than the highest high end guess here. The fact they didn't mention the clocks nor demo'd anything other than cinebench, isn't a good sign on those fronts. When it comes to management, pay as much attention to what they don't say as what they do.

When mgmt says Q2 or Q3 on something, 9 times out of 10 it's June or September. I give April very low odds.

Sorry, but I am in management and this release was very underwhelming to me. I hope that it was underpromise and end up overdelivering, but marketing never thinks like that. I was really hoping they'd put a marker out there Intel has no hope of surpassing. Here's to hoping I'm wrong though.

 

[Zapetu]

now the I/O die is not a little too big for what it is?

At minimum should be 64 PCI-E lines, 2 DDR4, 4 sata, 4 USB 3.1, 2 IF links and thats about it.

There's not enough pins in the socket for 64 PCI-E lanes. The reason AM4 only has 24 PCI-E lanes (16 for gpu +4 M.2 + 4 for chipset) even though every zeppelin has 32 lanes is that they ran out of pins. The reason why the APUs have even less is that they needed the pins for display out.

To be fair, I think it's just a typo and it should have been 32 (or 24) PCI-E lanes.

Personally I have to say that everything makes a lot more sense now than it did when we were talking about half SoC's with DDR4 MCs and IO splitted between dies or many other bifurcated variations. It was still interesting speculation even though it turned out to be wrong.

If there actually will be a Navi chiplet then it makes sense to put some display related logic (like a display engine) on the chiplet so that all chiplets would have the same pinout and interface with just an IF-link. As Tuna-Fish wrote, APU's use some (PCIe) pins for a display output and the same could be applied for the AM4 IO die. I think that there's no point to make different IO dies with very minor differences between them. It would make more sense to add all the necessary features to one IO die and then bin them for different SKUs. That Navi chiplet is still very much just speculation (comes from that AdoredTV rumor mill) but it would really help AMD in the OEM market. Even a 12nm (or 7nm) Vega chiplet would be a nice addition but I'm hoping it would be Navi. Still might be that it's CPU chiplet(s) only, for now at least. We really don't know for sure.

 

[itsmydamnation]

You're the only one in this thread that thinks the clock was that high. Your low end is even higher than the highest high end guess here. The fact they didn't mention the clocks nor demo'd anything other than cinebench, isn't a good sign on those fronts. When it comes to management, pay as much attention to what they don't say as what they do.

Yep thats why Ryzen 1800X released with a max clock of 3.5ghz

 

[Shivansps]

To be fair, I think it's just a typo and it should have been 32 (or 24) PCI-E lanes.

Personally I have to say that everything makes a lot more sense now than it did when we were talking about half SoC's with DDR4 MCs and IO splitted between dies or many other bifurcated variations. It was still interesting speculation even though it turned out to be wrong.

If there actually will be a Navi chiplet then it makes sense to put some display related logic (like a display engine) on the chiplet so that all chiplets would have the same pinout and interface with just an IF-link. As Tuna-Fish wrote, APU's use some (PCIe) pins for a display output and the same could be applied for the AM4 IO die. I think that there's no point to make different IO dies with very minor differences between them. It would make more sense to add all the necessary features to one IO die and then bin them for different SKUs. That Navi chiplet is still very much just speculation (comes from that AdoredTV rumor mill) but it would really help AMD in the OEM market. Even a 12nm (or 7nm) Vega chiplet would be a nice addition but I'm hoping it would be Navi. Still might be that it's CPU chiplet(s) only, for now at least. We really don't know for sure.

I have no idea from were i had 64 pci-e lanes on my mind. It is 32.

What i have a hard time figuring out is why AMD is launching 1 chiplets cpus whiout integrated video, just make a "Vega 5" chip, use it as igp in these CPU using the 2nd chiplet place. And launch as well it as reeplacement for HD5450, HD6450 (and its rebrands) at the ultra-low end zone, were the GT710 is. It just need 64bit DDR4 controller (for dgpus) and the IF link and thats petty much it. Thats more than enoght of a modern video display controller for these CPUs for non-gaming needs, and a excellent reeplacement of those ancient dgpus.

 

[Mopetar]

AdoredTV said, and I would agree, that AMD is likely reserving the most efficient chiplets for EPYC, and the highest frequency ones for TR.

Using the most efficient chips for EPYC certainly makes sense, but saving the highest frequency chips for TR doesn't necessarily make sense. As per the AT article, the chiplet shown on stage was estimated to use around 75W (less whatever the IO die needs) which suggests there's probably some additional headroom for higher clocks, even if the chip is at the edge of efficient scaling.

Since Ryzen appears as though it will use up to two chiplets, it's almost a certainty that ThreadRipper will use 4 chiplets across the board. If you put four chiplets similar to what we saw on stage, the power draw is already above 250W which was the previous top TDP for ThreadRipper parts.

From a certain perspective, it might not be a bad idea to use the chiplets capable of hitting the highest clock speeds as 8 core parts for an enthusiast gaming product. That allows AMD to sell twice as many CPUs with those characteristics and not have to worry too much about exceeding the capacities of existing motherboards and cooling solutions.

 

[PeterScott]

What i have a hard time figuring out is why AMD is launching 1 chiplets cpus whiout integrated video, just make a "Vega 5" chip, use it as igp in these CPU using the 2nd chiplet place. And launch as well it as reeplacement for HD5450, HD6450 (and its rebrands) at the ultra-low end zone, were the GT710 is. It just need 64bit DDR4 controller (for dgpus) and the IF link and thats petty much it. Thats more than enoght of a modern video display controller for these CPUs for non-gaming needs, and a excellent reeplacement of those ancient dgpus.

Cost? I would think they would want to charge a premium for them to recover they extra cost of an IGP. Which may simply drive up prices for those that really don't want the IGP.

Ryzen Desktop CPUs have been quite popular without IGP, and the higher end chips are often sold to people who aren't interested in IGP anyway.

I was wrong about them using chiplets on the desktop parts, but now that it is here, that free spot for more another CPU chiplet, or GPU chiplet definitely gives them some room to grow easily with the same design.

They can just stay at 8 core max for now, until they are swimming in high yield chiplets and/or Intel gets more competitive and simply add the second CPU chiplet and have 12 and 16 core parts.

Too bad we have to wait a lot longer for 7nm laptop APUs, because that is the part I really thought would stay integrated...

 

[Zapetu]

What i have a hard time figuring out is why AMD is launching 1 chiplets cpus whiout integrated video, just make a "Vega 5" chip, use it as igp in these CPU using the 2nd chiplet place.

This is still just speculation but if they're using the same organic package (edit: or at least the same basic layout, why would they otherwise put that one chiplet in the corner) for all AM4 SKUs (they could alternatively have different packages for different chiplet configurations) then all chiplets must have the same interface and pinout. That would also mean that all chiplets must be the same size (72-80mm² or the size of the "Rome CPU chiplet"). That Vega 5 chiplet using 12nm or 14nm would add something (at least a little bit) to the cost of a SKU but obviously AMD didn't think that it would be a good idea to add IGPs to all of their SKUs. Even Intel is now selling new SKUs with disabled IGPs. We still have very little information of the different variations of this AMD's chiplet design and we just have seen the most basic 8C version with one chiplet and an IO die.

There's one important thing to note, though. That AM4 IO die is big enough to support all cache coherency logic for two chiplets but still it could be used with just one chiplet and with no dummy die for mechanical stability. That really gives AMD more freedom and saves 7nm silicon for lower end SKUs. They could still release some SKU with 4C+4C configuration but they don't have to use two chiplets for most of the 8C parts. Once the yields get higher, this is going to be a huge benefit. I'm hoping that they could do the same with different EPYC and TR SKUs as well and there's no need for dummy dies in there either. Edit: And to be clear, I'm hoping that 16C TR could use just two chiplets and same could be true for 16C EPYC also. None of us know what the rules for the chiplet configurations are and we'll just have to wait and see. I'll admit, though, that it's more important for high volume (low price) parts (like 6C and 8C models) to save those precious 7nm chiplets than for TRs or EPYCs. Still having 2, 4 and 8 chiplet variations would be desirable.

 

[scannall]

While the Ryzen part was a bit lacking in information, it appears anyway that AMD is swinging for the fences. I'm looking forward to its release.

 

[Mopetar]

While the Ryzen part was a bit lacking in information, it appears anyway that AMD is swinging for the fences. I'm looking forward to its release.

It seems that they're still a ways away from launching Zen 2 as even EPYC was billed as "shipping mid-2019" so I can understand why there isn't a lot of concrete information yet. There's no point in releasing prices until you're ready to ship, and there's nothing to be gained giving Intel any more information about your intended product stack than you have to,

However, the demonstration gave us more than enough information, even if you have to read between the lines. A single Zen 2 chiplet is able to go toe-to-toe with the 9900K, so AMD has essentially closed to the IPC and clock speed gap with Intel. They also showed that their Ryzen 3000 CPUs have room for another chiplet on top of that.

Sure this was AMDs best benchmark so you can probably expect that Intel will still hold a performance advantage in some workloads, but AMD has shown that they've caught up, and even hinted that they might be able to pull slightly ahead. The specifics don't matter too much. The leaks from a few weeks ago might be correct or they might be wrong, but we know that AMD has something that's not just good, but even really great.

 

[beginner99]

Is there a point to Navi if it is only at 2060 performance when Radeon VII is around 2080 performance?

Exactly. And if Navi is supposed to be cheap some leaks said, then the difference in price to Radeon VII would be way too big and I doubt they can offer 16 gb of hbm2 for much cheaper than $699. The way Lisa Su kept mentioning how good it is for content creators (and not only gaming) makes me think it's not that good for gaming (maybe too much power?).

Cinebench R15 MT is some sort of best case benchmark for AMD because their SMT scaling works much better than Intels SMT there. Ryzen 2700x is almost on par with 9900k at 95W but is losing in other areas like games significantly.

Yeah that is my fear as well. AMDs SMT works very well in this bench and I do fully expect them to still be behind a 9900k in ST performance, mostly due to clocks.

On the otherhand Cinebench R15 MT was already so good on a 2700x maybe the changes to the uArch made a much bigger impact in other use-cases that aren't that good yet like gaming.