The WISC-SP01 RISC CPU....coming soon to a PC near you :)

[Sohcan]

I previously posted this in GH, but it didn't get much of a response...it might fit better here. Here's the CPU that my partner and I had to design from the ground-up for my computer architecture class.

Forget those offerings by Intel and AMD...the WISC-SP01 CPU features:
- 16-bit load/store MIPS-RISC architecture
- 100 MHz clock rate :Q
- 8 general purpose 16-bit registers
- 16-bit ALU with two-level carry-lookahead
- Barrel shifter for shifts and rotates (not that crappy serial shifter that the 8086 has )
- hard-wired PLA control unit
- 64KB DRAM memory
- 4KB direct-mapped cache
- ~15,000 logic gates

The only problem is that it lacks virual addressing and input/output support. You have to load the programs written in the assembly language directly into memory using the simulation program.

I might get around to pipelining it (it's already divided into pipeline stages, I just need to modify the control unit and add branch and data hazard detection units)...currently it's multicycle, taking 2-5 cycles to complete an instruction.

Here's some screenshots of a couple layouts that I took in Mentor, the CAD program we use to design and simulate the circuits:
Datapath & Control
CPU, cache & memory
Simulation of 4 instructions (we had to stare at these traces for dozens of hours to debug everything)

On a side note, is anyone here a student or professional in electrical/computer engineering? I'm actually majoring in comp sci/physics, but I might be going into computer architecture for grad school...

 

[Dark4ng3l]

Ok 1 question did you just design the "blueprint" of that cpu or did it get made(as in you made a physical chip that functions)

 

[Mucman]

That's pretty cool! I hope to be taking a course like that next semester. How high of a level course it that? The one I want to take is just a 200 level course and it will be using VHDL to simulate it.

 

[ERJ]

Heh, let me guess....CS 552

ERJ

 

[Sohcan]

Dark4ng3l: the design was done at the logic gate level (I'm not in electrical engineering ), which is simulated using the design program.

ERJ: LOL, good guess . Have you taken that class?

Mucman: It's a senior-level undergrad class, used as a follow-up to the lower-level digital logic design class...we did use VHDL to implement the control units. There's a lot more stuff covered in the class that we couldn't implement due to lack of time, such as pipelining, multiplication, division and floating-point arithmetic, input/output, and parallel processing.

 

[pm]

It puts it in perspective to think that this CPU is 15k gates total while one tiny little sub-sub-sub-sub block on a modern CPU would probably be an order of magnitude larger - like a block that handles the datapath of fills into one of several caches on a CPU.

I don't mean to belittle your CPU in any way - I did the same stuff back in college and it's a profound achievement to pull up some watch-window and watch the instructions get decoded, executed and retired. It's a beautiful thing and it's actually quite a difficult project for a semester or two project. If you got it working and passing regression, then I'm impressed (call me if you are ever looking for a job. )

But it does put the complexity of modern CPUs in perspective.

Patrick Mahoney
Intel Corp.

 

[Sohcan]

<< But it does put the complexity of modern CPUs in perspective. >>

No kidding...we were so happy when we were finally able to get an instruction to fetch, execute, and retire (after spending god knows how many hours designing the blocks, wiring them together, and debugging everything)...of course, once we achieved that, many more hours were spent debugging to make sure every instruction worked, along with the cache and memory controller. We wrote some small assembly programs to test all the instructions, but we were so relieved when the larger programs written by the professor worked at the project presentation. Even after taking this class, the complexity of modern CPUs still boggles my mind...we had two people working for about two months, compared to the dozens of engineers working for years on a modern design.

LOL, I guess I wouldn't mind working at Intel ...but I have to worry about grad school first.

 

[pm]

<< I have to worry about grad school first. >>

We probably want to take this offline (ICQ?) but why grad school? Far be it from me to attempt to dissuade someone from more education, but I have found that the reasons why people pursue a higher degree often are the wrong ones (higher pay, faster advancement, the idea that there's a 'glass ceiling' that you hit if you don't have one). There are plenty of good reasons for a graduate degree, but any of the ones that I listed are not them. But like I said, send me an email/ICQ if you are curious behind why I say this.