Various: AMD / HBM Analysis

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Feb 19, 2009
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Even if they can resolve it via drivers that waste less capacity, it looks bad to market an expensive flagship with 4GB when the competition has 6 and 12. Just the average joe gamer who wants the best, those numbers stick out very obvious.

If they claim they aren't limited to 4 stacks (there's no IMC, the logic layer is handling the stacked HBM) and any number can be used (within space limits), then why limit it to 4 and not 6 or 8?
 

Azix

Golden Member
Apr 18, 2014
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That quote doesn't claim its 4GB. Claimed one can use more than 4 or less than 4. It was real political and I assume that's because 4GB will be on a chip somewhere in their lineup.
 

Abwx

Lifer
Apr 2, 2011
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This in Ryan Smith article is not true :
Estimated DRAM
Power Consumption

AMD Radeon R9 290X 30W

NVIDIA GeForce GTX Titan X 31.5W
The number for the Titan is 46W.

Ryan is implying that the bus work at the same frequency, wich is not the case, the 290X has a 33% wider bus and power scale linearly with bus width.

Titan has a 25% narrower bus but at 50% higher frequency and power scale as a square of frequency, the net result is the 512bit MC/RAM consume 30% less, this of course at equal processes, wich is not the case for the MC...
 

Azix

Golden Member
Apr 18, 2014
1,438
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I'm wondering if we overestimate how big these stacks are. 35mm2. on a 4900mm2 area. I don't see why they would be putting only 4 on there. 5 x 7 mm on a 70 x 70 mm area. The illustration is not really representative.

 
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LTC8K6

Lifer
Mar 10, 2004
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4 is only for the first released version of HBM.

The new AMD card is apparently using the first version.

Later cards from NV and AMD will use version 2 of HBM, which will not have the limit of four.
 

LTC8K6

Lifer
Mar 10, 2004
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http://www.tomshardware.com/news/amd-high-bandwidth-memory,29116.html

Previously, there were no other options to boost performance other than to increase the frame buffer. There were no engineers working on solving this problem, but now with the way HBM can scale, AMD has put some of its own minds to work on finding more efficient ways to handle memory. It would seem the company is confident that 4 GB of HBM will rival the larger frame buffers that have been popular as of late.
 

LTC8K6

Lifer
Mar 10, 2004
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Let's not forget what Tonga introduced:
The end result is that GCN 1.2 introduces a new color compression method for its ROPs, to reduce the amount of memory bandwidth required for frame buffer operations. Color compression itself is relatively old – AMD has had color compression in some form for almost 10 years now – however GCN 1.2 iterates on this idea with a color compression method AMD is calling “lossless delta color compression.”

Since AMD is only meeting us half-way here we don’t know much more about what this does. Though the fact that they’re calling it delta compression implies that AMD has implemented a further layer of compression that works off of the changes (deltas) in frame buffers, on top of the discrete compression of the framebuffer. In this case this would not be unlike modern video compression codecs, which between keyframes will encode just the differences to reduce bandwidth requirements (though in AMD’s case in a lossless manner).

AMD’s own metrics call for a 40% gain in memory bandwidth efficiency, and if that is the average case it would more than make up for the loss of memory bandwidth from working on a narrower memory bus. We’ll see how this plays out over our individual games over the coming pages, but it’s worth noting that even our most memory bandwidth-sensitive games hold up well compared to the R9 280, never losing anywhere near the amount of performance that such a memory bandwidth reduction would imply (if they lose performance at all).

http://www.anandtech.com/show/8460/amd-radeon-r9-285-review/3
 

maddie

Diamond Member
Jul 18, 2010
5,131
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I'm wondering if we overestimate how big these stacks are. 35mm2. on a 4900mm2 area. I don't see why they would be putting only 4 on there. 5 x 7 mm on a 70 x 70 mm area. The illustration is not really representative.


Yes, but it says <70 x <70. Everyone keeps saying 70 x 70.
 

LTC8K6

Lifer
Mar 10, 2004
28,520
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This is possibly why the first Fiji card has 4gb of HBM?

AMD decided to go another direction and looked at going wide and slow since they were just looking for bandwidth. In this particular case they also got improved latencies, which wasn&#8217;t their primary goal. AMD created a passive interposer that has no active transistors. This allows for incredible densities due to the closeness of everything. With this design AMD was able to go from 32-bit on GDDR5 memory to 1024-bit width bus on HBM. The interposer is built by UMC and uses an older technology as it doesn&#8217;t need to be made using the latest fab technology.

http://www.legitreviews.com/amd-high-bandwidth-memory-detailed-with-joe-macri_163855
 

therealnickdanger

Senior member
Oct 26, 2005
987
2
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But seriously, AMD needs to get this show on the road. These monies are burning a hole in my pocket and the days are just crawling by...
 
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