Why Hammer doesn't need FSB?

[Bluga]

I know it's due to on die mem controller, however can anyone elaborate that? Thanks.

 

[Locutus4657]

The FSB is the link from the memory controller to the CPU, since that's on die that is eliminated. The Hammer replaces the traditional FSB with Hypertransport.

Originally posted by: Bluga
I know it's due to on die mem controller, however can anyone elaborate that? Thanks.

 

[YossI]

as mantioned above the defanition of the front side bus speed is the speed in which the CPU comunicates with the core logic, core logic being the north bridge.

sence the memory controler is on die, you can think of the front side bus as being the CPU speed.
i've heard from an AMD employ (on Recored) that the A0 stepping FSB is double and more (1400mhz as reprted ?) of that any motherboard offers today. Then I asked him wheather the FSB speed was the CPU speed and he said it is.

the real buty of the on-die memory controler is in MP configurations where the on die controler serves as dedicated front side bus to the memory.

 

[rimshaker]

The northbridge part of the chipset is now integrated within the cpu.

 

[CTho9305]

what is the bandwidth between processor memories? if you have 1 gig ram, can each processor access the whole 1 gig with the same latencies?

 

[Sahakiel]

If I remember correctly, the hammer processors access main memory via Hypertransport. I think what happens is that in MP setups, each processor has its own memory bank. Whether or not the seperate memory banks are actually the same physical memory duplicated on the chart or the data within it mirrored or whatnot, I don't know.
As for the FSB, I'm guessing overclocking your RAM up to 200mhz or more will finally see some tangible results. Especially since the Hammers debut with dual-channel DDR. Either that, or AMD did to the memory controller what Intel did to the P4.

 

[YossI]

in a MP congiration Hammer system each processor is assigned dimms of memory to comunicate with.
if a given processor asks for a memory adress that itself isn't connected to then the request goes through a HyperTransport to the processor that can comunicate with the memory module which holdes the adress.
this adds a few lathncy clocks to memory request. a very small price compared to SMP conifgeration which shares a fixed memory bandwidth to all processors to handel requests for memory or cahce coherency.

you can genraly think of the on die memory controler as a dedicated front side bus to the memory...

 

[Bluga]

Originally posted by: YossI
as mantioned above the defanition of the front side bus speed is the speed in which the CPU comunicates with the core logic, core logic being the north bridge.

sence the memory controler is on die, you can think of the front side bus as being the CPU speed.
i've heard from an AMD employ (on Recored) that the A0 stepping FSB is double and more (1400mhz as reprted ?) of that any motherboard offers today. Then I asked him wheather the FSB speed was the CPU speed and he said it is.

the real buty of the on-die memory controler is in MP configurations where the on die controler serves as dedicated front side bus to the memory.

Does that imply Hammer is running @ 1400MHz?

 

[CTho9305]

Originally posted by: YossI
in a MP congiration Hammer system each processor is assigned dimms of memory to comunicate with.
if a given processor asks for a memory adress that itself isn't connected to then the request goes through a HyperTransport to the processor that can comunicate with the memory module which holdes the adress.
this adds a few lathncy clocks to memory request. a very small price compared to SMP conifgeration which shares a fixed memory bandwidth to all processors to handel requests for memory or cahce coherency.

you can genraly think of the on die memory controler as a dedicated front side bus to the memory...

So this implies to me that you want threads to stick with their CPU as much as possible, as having them jump as load varies would add penalties while the required memory is copied.

 

[ShadowDJ]

Is it true that the memory controller can be interchanged? I've heard that It can be changed to support different memory types, is that true? I'm a bit confised as to how that would work. I'm just guessing they would have different versions of hammer with different memory controllers at the same time. Also, how would you overclock a hammer? (if that that's even a possibility)

 

[Locutus4657]

You will have to buy a new hammer to use a new type of memory. As far as over clocking, it's something I usually don't pay attention to, I suppose people will find a way though. They usually always seem to find away some how. Heck, it turns out Sony's "Copy Proof" CD's can be easily copied with the aid of a magic marker!

Originally posted by: ShadowDJ
Is it true that the memory controller can be interchanged? I've heard that It can be changed to support different memory types, is that true? I'm a bit confised as to how that would work. I'm just guessing they would have different versions of hammer with different memory controllers at the same time. Also, how would you overclock a hammer? (if that that's even a possibility)

 

[rgwalt]

Will AMD no longer use SMP type design for multiple processors?

Ryan

 

[Bluga]

bump.

 

[L3Guy]

Why Hammer doesn't need FSB

It really depends on what you think a FSB does. IMHO, any of these are "reasonable"

1. The FSB connects the CPU to the Memory controller.
In this case, hammer has a FSB on chip. Also, external memory controllers are possible, so the hypertransport bus can act as a FSB in the design.
2. The FSP connects the processor to its support chips.
Again, Hammer has a FSB.

On the other hand, neither K7 or K8 have a bus interface to the "northbridge". Bus implies a multiple device capable communication channel, while K7 and K8 have point-to-point channels. On the other hand, P3 did have a true bus topology, and allowed multiple processors access to the northbridge.

Will AMD no longer use SMP type design for multiple processors?

Because the multi-processor K8 can access memory on another K8, its not truly symmetric, having better access to memory on the local controller. Whether the MP software/hardware is aware of the difference between local and remote memory remains an open question.

Just my two cents.

Doug

 

[Locutus4657]

Nope, they will all be NUMA or Non-Uniform Memory Access. This design is better for scaling to large numbers of CPUs.

Carlo

Originally posted by: rgwalt
Will AMD no longer use SMP type design for multiple processors?

Ryan