Wow. Those are big dies.

[Mark R]

AMD quad core CPU dies

Look at that wafer (supposedly a real photo). It looks like each die is about 3/4" in both length and width. Am I right in thinking that each die appears to contain a 'standard' core and a 'mirror image' core, rather than there being alternate standard 'dies' and mirror image 'dies' on the wafer?

Looks like those are going to be real expensive.

 

[pm]

I came up with approximately 16.7mm x 17.6mm (assuming the wafer is 300mm. I counted 18 die wide by 17 die tall and did the division).

 

[swtethan]

16 wide and 16 tall


not all the chips are complete

but its about 17 mm in size

which is 3/4 of an inch or so :Q

 

[hans007]

Originally posted by: pm
I came up with approximately 16.7mm x 17.6mm (a wafer is 300mm and I counted 18 die wide by 17 die tall and did the division).

that sounds about right.

they will probably get horrible yields (which is why intel does it with 2 seperate die the odds of getting a defect on a single giant die is very large)


300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

 

[pm]

Originally posted by: swtethan
16 wide and 16 tall, not all the chips are complete

I agree that there's only 16x16 die... but we are trying to figure out the size of the die relative to the wafer... so we should count half die for purposes of figuring out the die size... no?

 

[TuxDave]

Yowch... looks expensive.

 

[myocardia]

Originally posted by: hans007
300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

 

[dmens]

Originally posted by: myocardia
This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

how big's the L2? standard conroe's have 4MB combined. bad cache lines can be disabled, so bad spots that fall on the L2 can be bypassed.

 

[myocardia]

They're supposed to be 4x512KB of L2, plus 2MB of L3, IIRC.

 

[liebremx]

Originally posted by: myocardia

Originally posted by: hans007
300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

 

[Hard Ball]

Originally posted by: liebremx

Originally posted by: myocardia

Originally posted by: hans007
300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

Well, it's not really a big loss. If you remember from AMD's earlier presentations, 4core and 2core dice will share the same cross-bar and other NB components; so it wouldn't be difficult to sell partially defective parts as <4core CPUs.

 

[myocardia]

Originally posted by: liebremx
[Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

The problem with your argument, though, is that none of the Conroe cores will have been tested until after they all been glued together. So, Intel will be in the same boat as AMD, as far as sometimes ending up with one bad core. My guess is that we might be seeing some tri-core processors for sale, at deep discounts, from both companies.

 

[liebremx]

Originally posted by: Hard Ball

Originally posted by: liebremx

Originally posted by: myocardia

Originally posted by: hans007
300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

Well, it's not really a big loss. If you remember from AMD's earlier presentations, 4core and 2core dice will share the same cross-bar and other NB components; so it wouldn't be difficult to sell partially defective parts as <4core CPUs.

Haven't seen those slides But yes, they must have thought about what to do with defective quads so they will probably sell them as you say.

 

[liebremx]

Originally posted by: myocardia

Originally posted by: liebremx
[Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

The problem with your argument, though, is that none of the Conroe cores will have been tested until after they all been glued together. So, Intel will be in the same boat as AMD, as far as sometimes ending up with one bad core. My guess is that we might be seeing some tri-core processors for sale, at deep discounts, from both companies.

Second picture in here suggests otherwise

Ability to match die for better bin splits

 

[pm]

The problem with your argument, though, is that none of the Conroe cores will have been tested until after they all been glued together.

There's a pre-package tester that uses structural testing to check the die prior to packaging. At Intel it's called the "ST2" or wafer sort test.

I'm not aware of any good free links to articles about this portion of the testing program... but there's a discussion of it in this IEEE article (which discussions the migration from functional test content to structural test content... there's a picture of a wafer sort tester on page 15): http://leitl.org/docs/intel/Mayberry%25...2.pdf#search=%22intel%20st2%20wafer%22

There was a paper presented at the ITC (International Test Conference) a few years ago which was pretty good - but you need access to a good library (with back issues of ITC's journals) or a subscription to IEEE Xplore to read it. Let me know if you want the details though, and I'll look it up.

 

[coldpower27]

A thought so considering the Quad Cores, so 65nm is not economical really and will be just to get them out there for Quad Core production.

 

[pm]

A thought so considering the Quad Cores, so 65nm is not economical really and will be just to get them out there for Quad Core production.

That depends on your definition of economical... if by "economical" you mean, "likely to be available at a mid to low level consumer price range" then you might be right. But if you mean "no one will make any money making them", then I don't think that will be the case at all.

 

[myocardia]

Originally posted by: pm

The problem with your argument, though, is that none of the Conroe cores will have been tested until after they all been glued together.

There's a pre-package tester that uses structural testing to check the die prior to packaging. At Intel it's called the "ST2" or wafer sort test.

I'm not aware of any good free links to articles about this portion of the testing program... but there's a discussion of it in this IEEE article (which discussions the migration from functional test content to structural test content... there's a picture of a wafer sort tester on page 15): http://leitl.org/docs/intel/Mayberry%25...2.pdf#search=%22intel%20st2%20wafer%22

There was a paper presented at the ITC (International Test Conference) a few years ago which was pretty good - but you need access to a good library (with back issues of ITC's journals) or a subscription to IEEE Xplore to read it. Let me know if you want the details though, and I'll look it up.

That's too cool. Thanks for the link. That's the first I've ever heard of that kind of a contraption. So, I guess we'll only be seeing deeply discounted tri-cores from AMD, huh?

 

[pm]

That's too cool. Thanks for the link. That's the first I've ever heard of that kind of a contraption.

I'm actually disappointed that there's not much out there that talks about it in more detail. I was a bit underwhelmed at what I could turn up with Google and terms like "intel wafer sort", "intel st2 sort" and others. It's not apparently a widely discussed thing - although the paper at ITC went into a fair bit of detail (I remember it fairly well because, as I recall, it won "Best Paper" that year). I have written tests for the ST2 at Intel used to test recent Itanium microprocessors. From personal experience, I can tell you that it's really cool... unless it's not doing what you want it to and you have to try to debug on it.

Also, as far as the die size, personally, I think it's big, but it's not THAT big... but maybe I hang around with Itaniums too much. My last project prior to my current one, was Montecito which is 596mm^2.

 

[Vegitto]

Originally posted by: pm

A thought so considering the Quad Cores, so 65nm is not economical really and will be just to get them out there for Quad Core production.

That depends on your definition of economical... if by "economical" you mean, "likely to be available at a mid to low level consumer price range" then you might be right. But if you mean "no one will make any money making them", then I don't think that will be the case at all.

I can guarantee you that NO company can survive without making profits .. Unless they have a monopoly, or produce multiple products (Microsoft, XBOX360), they just can't..

 

[coldpower27]

Originally posted by: pm

A thought so considering the Quad Cores, so 65nm is not economical really and will be just to get them out there for Quad Core production.

That depends on your definition of economical... if by "economical" you mean, "likely to be available at a mid to low level consumer price range" then you might be right. But if you mean "no one will make any money making them", then I don't think that will be the case at all.

Yeah, I mean likely available at the lower price ranges, I didn't mean they wouldn't make a profit on them. The die sizes here seem more realistic as the Chip Architect Slide of K8L/Rev.H predicted 150mm2 for a Quad Core.

 

[zephyrprime]

I wonder if there will be tri-core products since the defect rate is expected to be high? I don't think the cost will be as big a problem as many of you think because business will be buying these and they often budgets that are on a different scale than what we're used to. Businesses buy entire servers, not individual processors so the big cost of these processor is diluted by the rest of the hardware. And the cost of a 8-core machine with two chips may be less than the cost of a 8-core with 4 chips.

 

[BrownTown]

No, there will not be tri-core processors, that will just make too many different types of processors which confuses people. Defective quad cores will be sold as dual cores.

 

[CTho9305]

Have you seen what the 90nm dual cores look like? (Note that that's a 200mm wafer, not a 300mm wafer)

 

[TanisHalfElven]

Originally posted by: liebremx

Originally posted by: Hard Ball

Originally posted by: liebremx

Originally posted by: myocardia

Originally posted by: hans007
300mm^2 is giant. a conroe die is something like 140 mm for a 4mb one.

the amd cpu is supposed to be 4 x 512k cache,+ a shared 2mb cache. the ddr2 controller alone added an additionaly 20mm^2 on the am2 chips (in addition to whatever the ddr1 controller took) @ 90nm as well.

but 300mm^2 is gonna yield pretty badly especially with that many transistors. its made on the same process as the cell chip 65nm whcih is having awful yields (cell is a pretty large chip too) so it will be interesting to see how it works out.

This post makes absolutely no sense, hans. You're guessing that the AMD quad will be ~300mm², which you say is way too big, but then say that a Conroe die is 140mm². Isn't 140x2=280mm² pretty close to ~300mm² in your book, like it is in mine?

Yes they are BIG from die yields POV. A single fail in one of those dies and now you can't sell a quad core processor. Don't know if it would be possible to cut the die to end up with a dual core though.
Contrast that with making an MCM out of two Conroes: From the economics POV it is way better.

Well, it's not really a big loss. If you remember from AMD's earlier presentations, 4core and 2core dice will share the same cross-bar and other NB components; so it wouldn't be difficult to sell partially defective parts as <4core CPUs.

Haven't seen those slides But yes, they must have thought about what to do with defective quads so they will probably sell them as you say.

t'll prolly work out the same way grpahic cards do. disable a quad and sell the rest.