ECC was supported at release then disabled via agesa update. It was re-enabled in 1.0.0.5c, and as far as I am aware it will enable on all boards. Whether you can get error reporting or injection working is the wildcard, and as far as I know asus is the only brand that does handle both of those.Another interesting article about ECC support seeming to work in Linux with consumer AM5 motherboards (and specific AGESA versions).
ECC RAM on AMD Ryzen 7000 desktop CPUs :: sunshowers
Getting ECC memory working on desktop CPUs.sunshowers.io
I guess I'll give it another shot when I upgrade to Zen 5. The old 7950X (at maybe 105W) would make a good enough server chip.
They day before things are supposed to ship? is there still something wrong with the motherboards?It was somebody else said,m but it was changed to the 26th.
my concern with going brand new Raptor lake is there will be no more upgrades for that socket. Where as AM5 is just starting its life and you will see Zen 5 on it and maybe Zen 6.
If Zen 5 is coming out in 2024 and AMD said the socket is 2025+ that is pretty good guarantee.
Unless they are planning a new socket in 2024 which would be the opposite of what was said.
And considering their previous track record with AM4 I'm inclined to believe them.
Maybe I phrased it incorrectly, what I wanted to know is will the DGPU power down during normal desktop usage? That is what AMD told us. Probably it wont work with NVIDIA GPU.What in the world are you talking about ? I have the same GPU as AdamK47, a EVGA 3090TI FTW3, and its not a hybrid by any definition I have ever heard of.
How exactly Intel implements disabling of AVX-512? Is it just setting CPU flags? If it is just flags only, the AVX512 should work on AlderLake if forced to execute AVX512 code regardless of CPU flags. Similar to Zen1 and FMA4. Otherwise I would imagine they have to handle at decoder level to trap AVX-512 instruction and trigger exception. This would require the decoder to support disabling the AVX512 Instructions. I am not sure AMD would implement such a functionality to their decoder since many instructions are direct decode and not micro coded.The Real Question is... Will you be able to access the BIOS and Disable AVX-512 And run a few test for me?? Will you?? Uh?
Is micro code in the sense MicroCode ROM? To do that through micro code ROM, all the AVX512 instruction has to be micro coded. But I don't think all the AVX512 instruction are micro coded. Only complex and rarely used instruction are micro coded (I am more familier with AMD architecture than Intel so my understanding here might be incorrect). Most commonly used instructions are directly decoded to 1 or 2 u-ops. Only at decode stage the CPU will know about the instruction being decoded. Having another logic to already complex decode unit just for the purpose of disabling AVX512 seems wasteful. This is same for Intel and AMD.They do it through microcode. I think this is in later bios revisions. It also happens where there are e-cores present.
But this is a Zen 4 builders thread, nothing to do with Intel.
Haven't tried it. Asus SP values are still relevant when comparing 3DVcache CCDs by themselves and non-3DVcache CCDs by themselves.Thanks!
Have you tried this: https://community.hwbot.org/topic/210708-amd-ryzen-silicon-tester-quality-edhanced-worktool/
Still, what are you printing that needs so much paper? You could explore ways to prevent the printing. If you are doing it for personal use, why not just get something like a Kindle and read the stuff on that?I would have gone for recycled paper