Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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A///

Diamond Member
Feb 24, 2017
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N3E vs N5 provides 32% reduction in power draw at ISO performance.

This is pretty good If you think about It.
If we say that 7800XT had 225W just for the GPU alone, then 2/3 of units would be 150W, further reducing It by N3e process would result in 102W at 2430MHz.
Then there is still the possibility of higher clocks by fixing what went wrong in RDNA3, It really could end up faster than N22 while consuming a lot less.
RDNA3 would be best served with a 30% price cut to move units if it will come to that. With Intel improving their dgpu drivers ever so regularly and being committed to the next gen hardware I don't see AMD being the budget or mid choice anymore and they cannot compete at the high end with the 4090. AMD's lackadaisical approach to getting RDNA3 out and improving the experience with their software stack competing with Nvidia has not been a great show to consumers such as myself who were considering getting an RDNA3 card. I don't want to run the risk of a house fire getting an Nvidia card now. I'll wait for RDNA3.5 next year.
 
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Joe NYC

Platinum Member
Jun 26, 2021
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No it's just doing more effort for negligible packaging area gains.

Even if it helped only marginally to the OEMs, in order to increase adoption, it could end up worth it. Like I said, this is an area where AMD is lacking...

PHY swaps aren't quite that.

No you stick a fat PHY in and let it run lowest link states outside of heavy loads.

But that would need a full mask set, wouldn't it?
 

adroc_thurston

Platinum Member
Jul 2, 2023
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Even if it helped only marginally to the OEMs, in order to increase adoption, it could end up worth it
It won't increase the adoption since the upfront part cost is the main barrier to entry.
Like I said, this is an area where AMD is lacking...
They're doing more than well for that.
But that would need a full mask set, wouldn't it?
Masks aren't the expensive part and the design effort is minimal.
 
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A///

Diamond Member
Feb 24, 2017
4,352
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Not in the near future, that's for 10W parts AMD isn't building.
Ok. What's your opinion on Intel trialing it out? I know this is the zen thread but would this maybe be viable with low 10 watt packages or even higher power packages in future to compete with Apple without going the dismal apple route? Would you think there would be a breakthrough in packaging that allowed the LPDDR5X to be replaced if it failed instead of being soldered?
 

Joe NYC

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Jun 26, 2021
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OEMs are cautious with AMD only because if they can't supply enough stock to them.

Just as those concerns evaporated (H2 2022), when all the constrained disappeared, AMD client shipments collapsed. So that "cautiousness", on part of OEMs does not apply.

Let's see how things develop on the client side, now that the inventory correction also seems to be behind us. If AMD market share does not shoot up, then we can conclude it is something other than AMD's ability to supply, and if the product is equal or better than Intel, but market share does not reflect it, we will also know it is something other than that.

and what is a stacy.

That's a he.
 

A///

Diamond Member
Feb 24, 2017
4,352
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Just as those concerns evaporated (H2 2022), when all the constrained disappeared, AMD client shipments collapsed. So that "cautiousness", on part of OEMs does not apply.
That collapse was due to consumer demand falling flat on its face. Anyone who needed a new computer got one between early 2020 and early 2022. It wasn't just amd who suffered here.
 

A///

Diamond Member
Feb 24, 2017
4,352
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Let's see how things develop on the client side, now that the inventory correction also seems to be behind us. If AMD market share does not shoot up, then we can conclude it is something other than AMD's ability to supply, and if the product is equal or better than Intel, but market share does not reflect it, we will also know it is something other than that.
Given what adrock thuston has said Zen 5 seems like a real winner here. What I am more curious about it how fast processor releases will be now given that the pandemic is behind us and AMD can be on time but the whole cowos debacle is a new issue that needs to be nipped n the bud.

That's a he.
I'm going to assume this is one of those old school names some men have.
 

Joe NYC

Platinum Member
Jun 26, 2021
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No it's just doing more effort for negligible packaging area gains.

PHY swaps aren't quite that.

No you stick a fat PHY in and let it run lowest link states outside of heavy loads.

Interesting. So would be possible, if given enough power, that Strix Halo could outperform the equivalent desktop part.

It Zen 5 can conquer most of the bottlenecks inside the CCD, then something else becomes the bottleneck, external to the CCD. Given high bandwidth to CCD, and effectively 8 half channels or 4 full channels of memory bandwidth could be supplied to a single CCD.

Memory latency is typically a bigger problem than bandwidth, and we will see how it works out with Strix Halo, but the few instances that can use a lot of bandwidth, Strix Halo can outpace the desktop parts.
 

Joe NYC

Platinum Member
Jun 26, 2021
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Given what adrock thuston has said Zen 5 seems like a real winner here. What I am more curious about it how fast processor releases will be now given that the pandemic is behind us and AMD can be on time but the whole cowos debacle is a new issue that needs to be nipped n the bud.

It seems like RDNA 4 and Zen 5 will shorten the release cadence.

As far as CoWoS, it is not affecting AMD in the client space or server CPU. Only in datacenter GPU and some Xilinx products.

Intel has a similar 2.5D approach in its Meteor Lake and future server products. I am not sure how the industrywide bottleneck affects Intel specific implementation.

Going forward, AMD is bypassing CoWoS like 2.5D. Apparently with a combination of silicon bridges, that may come to RDNA5 and Venice and Fan Out implementations in client.

So it is really only Mi300 that is in the same boat. By Mi400, AMD will fully transition to the silicon bridges.

When the AI boom is over, there may be companies out there holding a CoWoS bag, with too much capacity and not enough demand.
 
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adroc_thurston

Platinum Member
Jul 2, 2023
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So would be possible, if given enough power, that Strix Halo could outperform the equivalent desktop part.
That really depends if USR on the SoC side gets more than 1 SDP.
The CCD uncore stop run cclk, but the SoC tile SDP runs fclk and the bandwidth delta is sizeable.
and effectively 8 half channels or 4 full channels of memory bandwidth could be supplied to a single CCD.
Depends on the SDP count.
Memory latency is typically a bigger problem than bandwidth, and we will see how it works out with Strix Halo
It has SLC for a good reason.
By Mi400, AMD will fully transition to the silicon bridges.
It still needs a gigantic CoWoS-L carrier to integrate all the HBM.
 

A///

Diamond Member
Feb 24, 2017
4,352
3,154
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It seems like RDNA 4 and Zen 5 will shorten the release cadence.

As far as CoWoS, it is not affecting AMD in the client space or server CPU. Only in datacenter GPU and some Xilinx products.

Intel has a similar 2.5D approach in its Meteor Lake and future server products. I am not sure how the industrywide bottleneck affects Intel specific implementation.

Going forward, AMD is bypassing CoWoS like 2.5D. Apparently with a combination of silicon bridges, that may come to RDNA5 and Venice and Fan Out implementations in client.

So it is really only Mi300 that is in the same boat. By Mi400, AMD will fully transition to the silicon bridges.

When the AI boom is over, there may be companies out there holding a CoWoS bag, with too much capacity and not enough demand.
Oh right you may be onto something there. I keep attributing covid to the late z4 launch but forgot that it would have affected rdna too. that may be why someone in another thread was comparing rdna5 to black well and why someone asked and then my inept reply because I'd overlooked that issue.

The ai boom will never be over. You're over simplifying what AI is if you only follow llms. That's amateur stuff on the scale of what's being done behind doors.
 

TESKATLIPOKA

Platinum Member
May 1, 2020
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That looks very nice tbh. was convinced it was plastic until I read the review's initial first few paragraphs. I do not like the offset track pad and the arrow keys jutting out.
I actually like that arrow keys are jutting out, not sure If It's usable or not.
I don't understand the meaning of offset track pad.

What I don't like is that small tilde key and the combined keys.
Oh well, you can't have It all.

edit:
I found a compact 14.5-inch laptop to my liking, but limited to RTX 4700.
ASUS Zenbook Pro 14 OLED (UX6404)
or Lenovo Yoga Pro 9i.
 
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TESKATLIPOKA

Platinum Member
May 1, 2020
2,381
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How does N3E compare to N4P? Or, if that direct comparison is not available, how does N5 stack up versus N4P? Then we can compare.
Here you go.
As the third major enhancement of TSMC’s 5nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks. N4P demonstrates TSMC’s pursuit and investment in continuous improvement of our process technologies.
BTW, why do you need N4P exactly?

edit: There are supposedly 3 different versions of N3E. Not sure which is used for Strix Halo. SemiAnalysis
 
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DrMrLordX

Lifer
Apr 27, 2000
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Here you go.

BTW, why do you need N4P exactly?
Thanks. I was too lazy to look that up myself. Napkin math when considering N3E 3-2 (it's the most-performant of the N3E variants) versus N4P:

~11% more dense
~19% more performant at isopower
~8.2% more power consumption at isoperformance (yes, that's right, N3E 3-2 has worse power characteristics than N4P . . . maybe)

Not sure how you can get improved performance at isopower but higher power consumption at isoperformance . . .? Too bad we'll probably never know if specific N3E-based products will use N3E 3-2 or 2-2.

As for N4P, it's probably the best mass-market (read: not N4X) node available from TSMC right now. Unless you count N3B but eh whatever, Apple is getting all of that anyway. In any case N3E should be TSMC's next good node. I just wanted to see how much better it would be than N4P.

As for what Strix Halo will use, ummmm probably something custom. So it may not precisely match the characteristics of any of those listed variants. But I'm guessing they'll use N3E 2-2 as a basis.
 
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TESKATLIPOKA

Platinum Member
May 1, 2020
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Can't they mix up all of these in a single design now?
I also remember they can with N3.

Hard to tell what that GPU die will use, but I still think It will use N3E 2-1. Yes, the scaling won't be that great considering It is GCD+IOD in one, but that power reduction is still needed for 40CU IGP and lowering production cost too.
N3E 3-2 would be great for IGP performance, but power consumption would be >120W just for the IGP itself. It would be problematic to cool It If you have another 2 power hungry CCDs on the same package.
 
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