Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[moinmoin]

Nah.
Same RTL as classic.

I see. What I read was that for AVX-512 Zen 5 would move to full 512-bit data path whereas Zen 5c would keep the 'double pumped' 256-bit data path as currently used in Zen 4. Wouldn't be the case if RTL is indeed the same.

 

[CouncilorIrissa]

Hypothetically would you rather have:
15% more 1T performance combined with 80% more MT performance (let's say it is 32 cores)
or
30% more 1T performance combined with 20% more MT performance (let's say it can't clock well in MT)
?

These are not random numbers but are also not a prediction of Zen 5 performance. Instead, these numbers are chosen because they are equal "expected improvement" if 80% of your work is 1T limited and 20% is perfectly parallel. Just trying to figure out preferences of what we would like Zen 5 to look like.

In your particular example if I were thinking about buying a 32-core chip, the it's likely that I'm making money off nT performance anyway, so a 13% (1.3/1.15) 1T gain might not be worth it.

But if you're not making money off nT, then I'd pick the option with higher 1T.

edit: on the other hand, most chips have no 1T OC headroom nowadays, whereas you're still able to gain some nT (at the expense of making your PC into a furnace)

 

[branch_suggestion]

Why would AMD move from a balanced core to a big, high IPC core? Well let's see what the competition is doing:

ARM is making a chungus core (X5+Neoverse derivatives)
Custom ARM has a few chungus cores (Apple since forever, QC Oryon)
Intel is making a chungus core (Lion Cove)
Heck, even RISC-V is starting to get near this level.

The aim, the core aim no matter what is maximum 1T IPC. Wider core does sacrifice perf/area but you can clock the thing lower for the same perf, which as long as IPC gains are higher than the power to drive the IPC, means better power efficiency.
Everyone seems to be happy with core counts as is outside of servers still increasing, so single threaded performance is the way to squeeze more out of progressively weaker node shrinks. Using smart design methodologies, you can still scale the same core for either max clocks/absolute performance or max area/power efficiency.

For whatever reason though, even with all the evidence presented on Z5 so far, some people are skeptical of it being bigger, or even as big of a leap at Z2>Z3.
People will say it is the node, but both Z2 and Z3 were both N7 class, a smaller leap than N5P>N4P.
nT perf doesn't always improve app performance, 1T always improves app performance.
For AMD to best compete, they let the shackles off the Zen5 team wrt core area, and let them push IPC as hard as they could, while still adhering to the same tenets of previous Zen cores, the gains cannot lead to excessive bloat or a mediocre improvement in perf/power.
It is the triangle of core attributes, Z5 sacrifices a bit of area efficiency to gain a huge amount of performance, with power improving as well but not by as much.

The aim is to have undisputed performance leadership to outcompete the new designs coming from vanilla/custom ARM and Intel.
Z5c does the same for more price/power conscious markets.
Zen is scalable, a word that AMD just loves to emphasise when they get the chance. With that said though, they do have a weakness remaining, that is a ULP island core ala Apple's E-core.
Their Cat successor will be coming one day to take on the very low power mobile market.

P.S. I find it amusing that many people are willing to cut ARM/Intel slack on hitting their ambitious targets but are so skeptical of AMD doing the same, when AMD is starting with the smallest core to build upon and sustained 25%+ numbered gen compound perf gains.
P.P.S. AMD has been exceptionally quiet, catching nearly everyone off guard with Z5 being pushed back to H2. ARM meanwhile sent that marketing blurb to Moorhead about X5 to try to gain some hype (real big NV seeding info to Forbes/Barrons vibes, aka showing the effects of comp pressure but trying to spin a win), Qualcomm did their X Elite thing ages before it actually goes on sale. Apple had to react to that, either that or QC rushed to beat them to the punch. Intel has been coy about LNC which regardless of how good/bad, is the right move.

 

[Glo.]

Where did you get the idea that Zen4 has a 6-way decoder?

From Zen1 to Zen4 the decoder is 4-way!

There is no leak suggesting that Zen5 will even have a 6-way x86 decoder.

Intel from Conroe to SunnyCove has a 4-way decoder. Only GoldenCove introduced a 6-way decoder.

All zens so far are 4 wide decode, just like bulldozer before it

I was thinking the other way around...

I meant 8 wide Dispatch and 6 way decode for Zen 5. Why did I wrote the other way around...?

We have leak for 8 wide dispatch, already. And 6 way decode is the only logical thing that would make Zen 5 core as fast as Adroc is touting.

Unless AMD went COMPLETELY NUTS, and made the decode even wider, of course.

6 way decode is technical SPECULATION, guys, in the context of rumors.

 

[Glo.]

I'm curious... what is your usecase for more than 8 high performance cores in the mainstream desktop world? Why should AMD spend double the silicon on cpu's? Even a lowly 7600 does admirably well in gaming these days, so I can't see why AMD should be shipping 16 cores as their 'standard'.

I'd take 8C Zen 6 +16 Zen 6C cores, without SMT, any day, over any other configuration of cores.

Assuming there is enough memory bandwidth to feed them., ofc.

 

[adroc_thurston]

and made the decode even wider, of course.

There are many other ways.

I'd take 8C Zen 6 +16 Zen 6C cores, without SMT, any day, over any other configuration of cores.

SMT isn't going anywhere.

Why would AMD move from a balanced core to a big, high IPC core? Well let's see what the competition is doing:

..

whoa now. mucho texto.
You can compact this essay into "they gotta kill Neoverse V very-very-very cleanly so that cloud favelas get in line and don't do any unwise moves".

 

[branch_suggestion]

whoa now. mucho texto.
You can compact this essay into "they gotta kill Neoverse V very-very-very cleanly so that cloud favelas get in line and don't do any unwise moves".

I didn't want to crush their hopes and dreams that directly.

 

[adroc_thurston]

I didn't want to crush their hopes and dreams that directly.

But it's kinda the point of large IPC bumps (and overall focus shifting towards dense performance as a baseline).

 

[branch_suggestion]

But it's kinda the point of large IPC bumps (and overall focus shifting towards dense performance as a baseline).

Performance density aka per socket perf is the kingmaker for sure, making the dense core to the baseline design is wise.
CPU area is only one part of a die overall, so you can mess with the proportion to hit the desired goal.

 

[Markfw]

Performance density aka per socket perf is the kingmaker for sure, making the dense core to the baseline design is wise.
CPU area is only one part of a die overall, so you can mess with the proportion to hit the desired goal.

Well, the way I see it, AMD will have the 1T performance king, the multicore performance king, and the dense but still pretty high performance king. They will have it all.

Desktop included. Not sure about mobile.....

 

[branch_suggestion]

Not sure about mobile.....

28w+ I expect them to lead, aka 95% of premium Windows laptop SoC's.
RDNA3.5 should presumably lead in GPU efficiency.

 

[DisEnchantment]

P.S. I find it amusing that many people are willing to cut ARM/Intel slack on hitting their ambitious targets but are so skeptical of AMD doing the same, when AMD is starting with the smallest core to build upon and sustained 25%+ numbered gen compound perf gains.

P.P.S. AMD has been exceptionally quiet, catching nearly everyone off guard with Z5 being pushed back to H2.

Folks have memory. So when leaks don't materialize they get skeptical. Zen 5 April launch was as real as Santa until last week, and people got their wallets pitchforks out.



Also there is no need to police people on what they want for their CPU core. 64 cores ? 128MB V cache? ... These discussions never go anywhere.

The reaction would have been different if folks don't present leaks as fact but as hypothesis back by something more concrete than trust me bro. Discussions would be more engaging versus assertive statements in the absence of actual fact.

 

[branch_suggestion]

Folks have memory. So when leaks don't materialize they get skeptical. Zen 5 April launch was as real as Santa until last week, and people got their wallets pitchforks out.

View attachment 92878

Also there is no need to police people on what they want for their CPU core. 64 cores ? 128MB V cache? ... These discussions never go anywhere.

The reaction would have been different if folks don't present leaks as fact but as hypothesis back by something more concrete than trust me bro. Discussions would be more engaging versus assertive statements in the absence of actual fact.

Anything before H2, according to AMD's official material would've been an early release.
Many of us fell for the meme, but all that matters is that it comes out on time and the thing is still going to deliver all the same.

 

[trivik12]

Have we historically have had companies say an year and then release early that year. Normally when companies say a product will release that year, one has to assume Q4 of that year. When its not, they will call out. Intel has been calling out Sierra Forest will release H1 2024(which means June 2024). If AMD had intended to release in early in the year they would have called it out that way. I remember reading Anandtech when Zen 4 released and it just mentioned 2024. So that is that. There is no delay here for sure.

 

[FlameTail]

28w+ I expect them to lead, aka 95% of premium Windows laptop SoC's.
RDNA3.5 should presumably lead in GPU efficiency.

Well they better make substantial improvements, because this 780M curve looks ridiculous with how flat it is.

 

[adroc_thurston]

View attachment 92886
Well they better make substantial improvements, because this 780M curve looks ridiculous with how flat it is.

That was tested with a single-channel memory.
Single-channel G14 2023 SKU (that's like DDR5-5600).
16+0, the American one.
Funny bit of trivia!

Also, again, Adreno isn't a GPU, it can't run anything.
No drivers and very hacky h/w-side feature support in general.

 

[branch_suggestion]

That was tested with a single-channel memory.
Single-channel G14 2023 SKU (that's like DDR5-5600).
16+0, the American one.
Funny bit of trivia!

Also, again, Adreno isn't a GPU, it can't run anything.
No drivers and very hacky h/w-side feature support in general.

Yep, vs dual-channel (quad but I digress) LPDDR5X-8533.
Considering RDNA3 clocks to the moon with enough power, that slide shows an obscene bandwidth bottleneck.
Bad Qualcomm, bad!
And they avoid benchmarking anything that isn't a glorified mobile benchmark, like video games.

 

[FlameTail]

That was tested with a single-channel memory.
Single-channel G14 2023 SKU (that's like DDR5-5600).
16+0, the American one.
Funny bit of trivia!

Interesting. I didn't know this. Qualcomm is being sneaky!


Here is chart from Geekerwan

Also, again, Adreno isn't a GPU, it can't run anything.
No drivers and very hacky h/w-side feature support in general.

Adreno is the child of your beloved AMD, who gave it up to adoption in difficult times long ago. Fun fact: A D R E N O is an anagram of R A D E O N

 

[adroc_thurston]

Adreno is the child of your beloved AMD

Well it was, Qualcomm received full Xenos IP, DX10-compliant even (kinda) and made it a eunuch (they never used the ATi shader cores).
It's very good for phones but it's not a real desktop-class GPU IP.

It wasn't difficult times either, Ruiz saw no real future in merchant GPU IP licensing (and this was like the only time he was right, see the fate of Imagination).

 

[Khato]

Indeed, pretty sure that the primary application for a strong GPU is gaming, not synthetic benchmarks. Intel has done an excellent job of demonstrating that doing well on synthetic benchmarks does not translate to doing well in actual games. Heh, that and there's a reason why their choice of synthetic benchmarks are those that are from the smartphone realm.

 

[adroc_thurston]

Indeed, pretty sure that the primary application for a strong GPU is gaming, not synthetic benchmarks. Intel has done an excellent job of demonstrating that doing well on synthetic benchmarks does not translate to doing well in actual games. Heh, that and there's a reason why their choice of synthetic benchmarks are those that are from the smartphone realm.

Yeah, Gen12 is really good at TimeSpy and nothing really else.

 

[poke01]

Arch people jumped the ship en masse.

Mm I wonder where they went. 😝

 

[FlameTail]

Mm I wonder where they went. 😝

...

 

[HurleyBird]

More MLID. Claims that Z5 is still strong, but not as strong as originally intended due to bugs. Reasserts he considers the 30%+ people dead wrong.

Well, he was first out the gate with Z5 delay, and generally speaking hype trains are ultimately derailed far more often than they are realized.

 

[adroc_thurston]

Claims that Z5 is still strong, but not as strong as originally intended due to bugs.

Why can't ebeggars put any concrete product numbers out.
Half the industry knows Turin skt perf, why can't ebeggars do it.

Reasserts he considers the 30%+ people dead wrong.

Yea it's higher.