Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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soresu

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Dec 19, 2014
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BUT, Intel better get off their duff and make a competing product soon, before AMD turns into the "old" Intel.
We know that Zen5 was in planning months before Zen2 was released in 2019 from an interview early that year, so we can assume at the least that they probably already have Zen6 fairly well in focus now, and with Zen7 on the drawing board regardless of what Intel does.

Plus Intel are still being competitive enough in IPC (if not perf/watt for now) for AMD to stay on their toes.

Honestly I'm more worried about GPU future with R&D split between 2 different µArchs, AMD still not managing to retake the perf crown from nVidia and now Intel on the scene as a potential contender too.
 

DisEnchantment

Golden Member
Mar 3, 2017
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And yes, it's still 8 core CCDs for full-fat Zen 5.
Even with this, CCD seems a bit too big for AMD, ~100mm2 is quite big.
Indeed ~100mm2 is too big if going for a 12C CCD going by current AMD's philosophy.

The core size increase from Zen 2 to Zen 3 was ~35%, and the core logic itself (without L2 and L3) was a ~40% increase.
Zen2 to Zen 3 is a modest increase in core area, around 15% (~15%+ MTr) (from Locuza annotation of actual die shots) and Zen 3 to Zen 4 is another 18% area (+120% MTr)
2.83mm2 Zen 2 --> ~52 MTr/mm2
3.24mm2 Zen 3 --> ~52 MTr/mm2
2.84mm2 Zen 4 --> ~99 MTr/mm2

Zen 4 is quite poor from gains per MTr added. But 2xL2, AVX512, ROB, BTBs, etc. took quite a chunk of that added area.
At best I expect for the Core only 20% gain for Zen 5, and rest same.
Same L2, Same L3, Same SMU, Same TSVs, Same Debug/JTAG/BIST block.
Which should bring CCD to 73mm2, around 10% gain on Zen 4.

A more aggressive architecture change with +25% bigger core with +25% L2 will take the CCD to 77mm2, or +16% Area gain over Zen 4.

However, Zen 3 has shown that AMD can optimize some blocks to be smaller and more performant, so the rework of various Zen 5 blocks won't necessarily result in size increase of each block in a core, could be opposite too. Locuza has details on such blocks which had a reduction in size in Zen 3 over Zen 2.
N4P could help with a some gains in density (something like the N6 PS5 SoC vs N7 SoC, quite a good reduction in size and power with this update)
If the IFOP PHY would be routed through an RDL on package instead of substrate, the beach head could be smaller.

Curious about the IFOP interconnect more than anything at the moment. This is one of the key driver for scalability and efficiency.
In terms of MTr/core Zen 4 at ~380MTr is still behind Apple's contemporary big cores. A 20% increase with Zen 5 would bring it on par and 25% bigger core is going to be on the higher side of the estimation (each core+L2 would reach half a billion XTor with N4)
 
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Kaffeekenan

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Jan 6, 2022
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I'm very certain these core counts are correct, I heard them a few months ago now. I'm also dead certain of who Jim's second "source" is as well - the one that said it was 128c and 192c - and trust me if I were to say who it almost certainly is you'd believe those core counts too.

Anyway at this point I'm also pretty certain about some other info as well, which is making me VERY excited for Zen 5 now.

Can you give us a tiny hint what you are so excited about Uzzi? Like is it about the configuration of the CPU or the IPC or efficiency or release date or what?
 

TESKATLIPOKA

Platinum Member
May 1, 2020
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Can you give us a tiny hint what you are so excited about Uzzi? Like is it about the configuration of the CPU or the IPC or efficiency or release date or what?
1. only 8C16T Zen5 CCD means they won't increase core count
2. process will be most likely 4nm
3. frequency will improve by ~5% to hit 6GHz in my opinion
What's left is only IPC. If they optimized Zen5 arch heavily, then perf/W should be noticeably better too.
The question is how much does IPC increase? For a significant increase of 20%, you need a lot bigger core than Zen4.
 

soresu

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Dec 19, 2014
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The question is how much does IPC increase? For a significant increase of 20%, you need a lot bigger core than Zen4.
Speculation puts it at least moving from 4 wide to 6 wide.

Papermaster seemed to be all but confirm that future cores were going wider in an interview last year that also covered Zen5 and his confidence in its potential - though it doesn't necessarily mean that he was talking about Zen5 when talking about future width of the core.

At some point though the low, mid and high hanging fruit of 4 wide µArchs are going to be gone and wider is the only way forward to set the foundation for a future core roadmap.
 

DisEnchantment

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Mar 3, 2017
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Can you give us a tiny hint what you are so excited about Uzzi? Like is it about the configuration of the CPU or the IPC or efficiency or release date or what?
Unfortunately there is barely any info in the open to even guess anything. Nothing we hear can be considered reliable. I heard from someone that Zen 5 is a reset of core and SoC architecture at AMD with a broader impact than the original Zen program. But that's about it, no specifics, not even an inkling whether this is remotely true.
Speculation puts it at least moving from 4 wide to 6 wide.

Papermaster seemed to be all but confirm that future cores were going wider in an interview last year that also covered Zen5 and his confidence in its potential - though it doesn't necessarily mean that he was talking about Zen5 when talking about future width of the core.
Papermaster was talking about Zen 5 during FAD 2022, just that "repipelined front end and wide issue". That's it. 😩
 

maddie

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Jul 18, 2010
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Unfortunately there is barely any info in the open to even guess anything. Nothing we hear can be considered reliable. I heard from someone that Zen 5 is a reset of core and SoC architecture at AMD with a broader impact than the original Zen program. But that's about it, no specifics, not even an inkling whether this is remotely true.

Papermaster was talking about Zen 5 during FAD 2022, just that "repipelined front end and wide issue". That's it. 😩
These are the pivot points that give us Bulldozer and P4 type products. Fraught with risk.
 
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Ajay

Lifer
Jan 8, 2001
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Unfortunately there is barely any info in the open to even guess anything. Nothing we hear can be considered reliable. I heard from someone that Zen 5 is a reset of core and SoC architecture at AMD with a broader impact than the original Zen program. But that's about it, no specifics, not even an inkling whether this is remotely true.

Papermaster was talking about Zen 5 during FAD 2022, just that "repipelined front end and wide issue". That's it. 😩
Yes, kind of frustrating. AMD , Nvidia have Really cranked down on public leaks. Takes some inertia away from the enthusiast crowd - but we aren’t the ones that need to be impressed anymore.
 

NostaSeronx

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Sep 18, 2011
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These are the pivot points that give us Bulldozer and P4 type products. Fraught with risk.
Should be noted that Netburst and Bulldozer had issues with the nodes from two different angles.

Netburst => 130nm -> 90nm was okay, but 90nm -> 65nm was not okay. Intel wasn't willing to pay for transition to other transistors so early. Especially, when P3/PP/PM->Core->Core 2 was a thing. // Hardware Physics
Bulldozer => 65nm Bobcat/Bulldozer prototype the new tools worked, but when shifted to 45nm/32nm they didn't work. Which lead the Bulldozer team to roll back to Greyhound(K8H(pre-K9 cancel) and K9(post-orig K9 cancel)) design methodologies. Which is why Bulldozer looked like Greyhound/Greyhound+/Husky in structure features and not like Bobcat/Jaguar/Zen. // Software Issues in regards to new nodes.

Zen5 is likely not to have such risks in prior-AMD grounds up. TSMC is structurally sound and not getting spinned out or bleeding cash to get FinFETs out. AMD isn't tossing Chief Zen architect/Chief technology officer out of the company or upgrading them to a higher job position unrelated to the new Zen core. The initial plan of Zen5 is not changing it is launching.

Major ALU-up&FPU-up iterations it should be like:
Bobcat -> Zen -> Zen5
 
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moinmoin

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Jun 1, 2017
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Honestly I'm more worried about GPU future with R&D split between 2 different µArchs, AMD still not managing to retake the perf crown from nVidia and now Intel on the scene as a potential contender too.
Partly off topic in this thread, but for AMD server remains the clear primary focus. There both the CPU (Genoa, Bergamo, Siena) and GPU (MI250, MI300) development is very promising and improvements seem to appear unabated.

Consumer space is more mixed. AM5 so far is not the clear upgrade over AM4 it could have been by offering a chip with more than 16 cores. And RDNA3 failed to meet AMD's own prior promises for whatever reason which points to issues in communication and/or execution. These I ascribe to not a lack of capability but a lack of focus or necessity, which I would hope AMD will want to resolve over time.
 
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Joe NYC

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Partly off topic in this thread, but for AMD server remains the clear primary focus. There both the CPU (Genoa, Bergamo, Siena) and GPU (MI250, MI300) development is very promising and improvements seem to appear unabated.

Consumer space is more mixed. AM5 so far is not the clear upgrade over AM4 it could have been by offering a chip with more than 16 cores. And RDNA3 failed to meet AMD's own prior promises for whatever reason which points to issues in communication and/or execution. These I ascribe to not a lack of capability but a lack of focus or necessity, which I would hope AMD will want to resolve over time.

On the client side, before AMD goes to more than 16 cores, IMO, there is not even a point to go from 8 to 16 unless / until there are communications links fast enough to have low core to core latencies, quick access to each other's caches.

While Zen 5 is still a mystery, as far as chiplet to chiplet communications, Mi300 is enough of a hint that something will come to the client that will borrow heavily from Mi300, Mi400.

AMD will have a logic CPU chiplet that is stackable on top of a base, consisting of I/O, analog and SRAM, so half of the problem is solved, half of the resources needed will already be spent. So the client side will be able to grab these and make a use of them.

BTW, that Jim / Adored video mentioned the huge number of CPU chiplet that AMD is making and sharing between server and client. If past can predict the future, I think AMD intends to share these top of the stack CPU chiplets, possibly across the board from datacenter GPU, server CPU, clinet CPU and even notebook CPU.

It remains to be seen which core generation will make this sharing to happen...
 
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yuri69

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Jul 16, 2013
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What's left is only IPC. If they optimized Zen5 arch heavily, then perf/W should be noticeably better too.
The question is how much does IPC increase? For a significant increase of 20%, you need a lot bigger core than Zen4.
Zen 4 is still a 4-way machine like Bulldozer (or Conroe!) when the uOP cache doesn't hit. Intel went 5-wide with Sunny in 2019 and 6-wide with Golden in 2021. A new design of 2024 should be wider than Bulldozer, Zen 1, or Conroe. That should bring gains in situation when the uOP cache doesn't provide the necessary backing.

The same applies to the chiplet packaging tech. They are generally still on the 2010 tech having implications for latency and power.

Frequency could go up if AMD lets their processors eat more power. Turin got TDP up to 600W which gives us an indication.
 

TESKATLIPOKA

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May 1, 2020
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Zen 4 is still a 4-way machine like Bulldozer (or Conroe!) when the uOP cache doesn't hit. Intel went 5-wide with Sunny in 2019 and 6-wide with Golden in 2021. A new design of 2024 should be wider than Bulldozer, Zen 1, or Conroe. That should bring gains in situation when the uOP cache doesn't provide the necessary backing.

The same applies to the chiplet packaging tech. They are generally still on the 2010 tech having implications for latency and power.

Frequency could go up if AMD lets their processors eat more power. Turin got TDP up to 600W which gives us an indication.
I also expect Zen5 to be wider than Zen4.
As you said, If AMD wanted then by enabling more power they can increase clocks in MT, but that's just not worth the increased power consumption.
Even that 170W TDP(230W PPT) is not worth It and they were criticized for It, because It provided a ~10% boost in performance, but efficiency was hurt a lot.
 
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eek2121

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Aug 2, 2005
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Partly off topic in this thread, but for AMD server remains the clear primary focus. There both the CPU (Genoa, Bergamo, Siena) and GPU (MI250, MI300) development is very promising and improvements seem to appear unabated.

Consumer space is more mixed. AM5 so far is not the clear upgrade over AM4 it could have been by offering a chip with more than 16 cores. And RDNA3 failed to meet AMD's own prior promises for whatever reason which points to issues in communication and/or execution. These I ascribe to not a lack of capability but a lack of focus or necessity, which I would hope AMD will want to resolve over time.

AM5 is still early on in terms of lifecycle. Lots of people on the Intel side went with DDR4 initially with Alder Lake, for comparison.

You also have to remember that the incentive to mine crypto has evaporated, causing a huge drop in demand for GPUs.

I wouldn’t say AMD is ‘server-focused’ per say, it is just that the performance targets for server/cloud scale all the way down to mobile. Perf/watt and per/$ are important across all segments.
 

Geddagod

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Dec 28, 2021
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Zen 4 is still a 4-way machine like Bulldozer (or Conroe!) when the uOP cache doesn't hit. Intel went 5-wide with Sunny in 2019 and 6-wide with Golden in 2021. A new design of 2024 should be wider than Bulldozer, Zen 1, or Conroe. That should bring gains in situation when the uOP cache doesn't provide the necessary backing.

The same applies to the chiplet packaging tech. They are generally still on the 2010 tech having implications for latency and power.

Frequency could go up if AMD lets their processors eat more power. Turin got TDP up to 600W which gives us an indication.
Zen 3, and Zen 4 are designed in mind with this weakness. Zen 4 has >50% larger uOP cache than GLC, while Zen 3 was around the same size as GLC.
And Zen 4 is just as wide as GLC past the decoder IIRC
4 wide decode isn't "old" tech... they have done great on IPC by staying on 4 wide, and if you look in chips and cheese article on Zen 3 architectural bottlenecks, you see most of their weaknesses was ROB size, (improved with zen 4) FP regs (improved with zen 4), and load and store system (improved with zen 4). And Zen 3 with 4 wide decode is ~SNC which is 5 wide, and Zen 4 with 4 wide decode is ~GLC which is 6 wide decode, in terms of IPC.

And iFOP is great for what AMD does with chiplets. Because latency across chiplet's isn't what AMD is aiming for anyway, if they were they could focus on larger CCDs like what Intel is doing. And it's not like they simply can't, 5nm yields are great on TSMC at this point... instead they focus on good innner-CCD latency.
And sure, maybe with an active interposer will net you better latency or lower power consumption anyway, but AMD's chiplet method isn't focused much on across chiplet latency, and I believe power consumption across chiplets isn't any huge contributor to power consumption in AMD server chips regardless.
And lastly old tech is cheap tech. While I believe eventually AMD will switch off iFOP, I think the cost benefits are too high, and performance benefits too low, for iFOP to be replaced by Zen 5, and maybe even Zen 6.
 

Mopetar

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Jan 31, 2011
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On the client side, before AMD goes to more than 16 cores, IMO, there is not even a point to go from 8 to 16 unless / until there are communications links fast enough to have low core to core latencies, quick access to each other's caches.

Intel can actually hang with AMD in MT workloads now, and while they certainly have an efficiency edge there are plenty of people who don't care about such things.

The kind of people who would want a 24-32 core desktop CPU are those who are probably running rendering software that will gladly scale beyond 16 cores. Core to core latency doesn't matter much in those cases.

There are plenty of workloads that wouldn't care if AMDs solution to offering a 24-core CPU was just adding another chiplet anymore than they would about AMD putting 12 cores on a CCD.

Just don't expect it to be cheap assuming it does exist. AMD would likely try to maintain pricing based on the number of cores similar to the previous generation and use this as an excuse to have a $1,000 CPU. But it's less expensive that Threadripper so some people will buy it.
 

Joe NYC

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Intel can actually hang with AMD in MT workloads now, and while they certainly have an efficiency edge there are plenty of people who don't care about such things.

The kind of people who would want a 24-32 core desktop CPU are those who are probably running rendering software that will gladly scale beyond 16 cores. Core to core latency doesn't matter much in those cases.

There are plenty of workloads that wouldn't care if AMDs solution to offering a 24-core CPU was just adding another chiplet anymore than they would about AMD putting 12 cores on a CCD.

Just don't expect it to be cheap assuming it does exist. AMD would likely try to maintain pricing based on the number of cores similar to the previous generation and use this as an excuse to have a $1,000 CPU. But it's less expensive that Threadripper so some people will buy it.

There are images out there of the IO Die analysis, and the one for Zen 4 desktops has 2 links. So there is no possibility of just adding another CCD. The inner workings of the MCM would have to change and new IOD would have to be created.

One thing AMD could do is use RDL, like Navi 32/33 uses. That technology is cheap enough to use before AMD uses something with hybrid bond.

Total size of Navi31 between GDC and 6 MCD would be in the same ballpark as 1 IOD + 4 CCDs. RDLs, if built with more layers, could allow for lower latency, higher bandwidth and lower power than SerDes. Possibly having a mesh connection between all the dies. But I don't know how it would scale to EPYC.

Back to my original point: in gaming (larger market than CPU rendering), both Intel and AMD are stuck at 8 cores (with some extra cares possibly hanging off on the side not contributing meaningfully). Which is why I think we first need 16 cores able to meaningfully contribute to the first 8 before going to more than 16.
 
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Geddagod

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But I don't know how it would scale to EPYC.
Probably the biggest problem with all the crazy Zen 5 rumors and speculation...
Is how they scale into 8 or even more CCDs while also remaining cost effective

Something interesting though is that there's speculation that Zen 6 would work foremost on cache changes as well as building on Zen 5, and that got me thinking that perhaps crazier chiplet designs might be developed there as cost decreased currently and the near future.
 

DisEnchantment

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Mar 3, 2017
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Not much of improvement judging by the rumoured 6000mt/s specs.
I thought they eventually switch to some kind of active interposer (Zen 6? )
You meant this slide below?


Note 1 in the slide above seems to suggest that the next gen SP5 part can attain DDR5-6400 frequencies, which is a decent bump. DT will likely go beyond that.
However in Zen 4, fclk and mclk are not 1:1. So higher DDR5 speed does not really mean a higher fabric clock.
Due to the fabric clock limit, at max ~2GHz currently, there is a threshold beyond which increasing the RAM speed has no impact on the memory latency.
IFOP clock would have likely been capped at 2GHz since Zen 2 due to insertion losses and the high 2pJ/bit energy usage.

They don't really need an interposer to improve this and on package RDL in the N31 MCDs seems good enough.
It seems AMD got 0.4pJ/bit on the N31 RDL fanout links compared to 0.2-0.3 pJ /bit for GUC GLink. I did see 64 Gbps links on LinkedIn mentioned for new GMI.

Going forward, if Strix being chiplet is really a thing, they are going to absolutely need a new interconnect considering Dragon Range is idling at 10W (granted Power Gating is not as fine grained as in the purpose built Mobile APU and not sure if there is scaling of the fclk and lanes as per the workload)
 

Joe NYC

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Jun 26, 2021
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Probably the biggest problem with all the crazy Zen 5 rumors and speculation...
Is how they scale into 8 or even more CCDs while also remaining cost effective

Something interesting though is that there's speculation that Zen 6 would work foremost on cache changes as well as building on Zen 5, and that got me thinking that perhaps crazier chiplet designs might be developed there as cost decreased currently and the near future.

Genoa has 12x 8 core CCDs
Bergamo has 8x 16 core CCDs

Going to Zen 5 (speculating)
Turin: 16x 8 core CCDs
Bergamo+1: 12x 16 core CCDs

Zen 4 IOD die has 12 links to CCDs, so it would need to go up to 16 for Zeb 5 Turin using current technology.

Not being able to share cache between CCDs is a limitation of current technology (SerDes, IFOP). Even more so with Milan-X and upcoming Genoa-X. Because it will have ~1.25 GB of SRAM, which could offer even greater performance uplift if it was easily shareable.

BTW, it is interesting that AMD hides these details (very effectively) on the CPU - Zen 5 side, while sharing info on Mi300 datacenter GPU side...
 
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eek2121

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Aug 2, 2005
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Not that I'll think it will happen, but could AMD create a CPU with three chiplets for AM5?

Not likely, there simply isn't enough space. Some folks have attempted a mockup, but mockups ignore the electrical connections, and more importantly, the distance between those connections. For AMD to increase core count they would have to do one of the following:
  1. decrease the CCD size.
  2. decrease the IOD size.
  3. stack low performance 'small' cores on top of one of the dies. (not likely, heat is an issue)
  4. Use a 'hybrid' design.
  5. move to a monolithic die.
  6. Use a dense process
  7. Some combination of above.
 
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